公开(公告)号：US20230307071A1

公开(公告)日：2023-09-28

申请号：US17701320

申请日：2022-03-22

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Yu-Chung Lien ,  Ravi Kumar ,  Jiahui Yuan ,  Bo Lei ,  Zhenni Wan

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/3404 ,  G11C16/102 ,  G11C16/26

Abstract: The memory device includes a plurality of memory cells, which include a first set of memory cells and a second set of memory cells. A controller is in communication with the memory cells. The controller is configured to, in a first programming pass and then a second programming pass, program the memory cells of the first and second sets to respective final threshold voltages associated with a plurality of programmed data states. The controller is further configured to, in the first programming pass, verify the first set of memory cells at a first set of checkpoint data states and verify the second set of memory cells at a second set of checkpoint data states that is different than the first set of checkpoint data states.

公开(公告)号：US20220392552A1

公开(公告)日：2022-12-08

申请号：US17340826

申请日：2021-06-07

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Yu-Chung Lien ,  Deepanshu Dutta ,  Huai-Yuan Tseng ,  Ravi Kumar

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10

Abstract: A method for programming a memory block of a non-volatile memory structure, wherein the method comprises, during a program verify operation, selecting only a partial segment of memory cells of a memory block for bit scan mode, applying a sensing bias voltage to one or more bit lines of the memory block associated with the selected memory cells, and initiating a bit scan mode of the selected memory cells.

公开(公告)号：US20230197173A1

公开(公告)日：2023-06-22

申请号：US17554321

申请日：2021-12-17

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Prafful Golani ,  Ravi Kumar

IPC: G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/26

Abstract: A method for performing a program verify operation with respect to a target memory cell in a memory structure of a non-volatile memory system, wherein the method may comprise determining a location of the target memory cell within the structure and, based upon the determined location of the target cell and with respect to each programmable memory state: (1) applying a first sense signal at a first point in time, and (2) applying a second sense signal at a second point in time, wherein a time interval between the first and the second points in time is equal to a predetermined optimal time period plus or minus an offset parameter time value.

公开(公告)号：US11342035B1

公开(公告)日：2022-05-24

申请号：US17102657

申请日：2020-11-24

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Deepanshu Dutta ,  Ravi Kumar

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/30 ,  G11C16/10 ,  G11C16/08

Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells each connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and the strings determines a program lower tail voltage of a distribution of the threshold voltage following a first program pulse. The control circuit calculates a second program voltage of a second program pulse based on the program lower tail voltage and applies the second program pulse to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells such that the distribution of the threshold voltage of the memory cells have a desired program lower tail voltage without further program pulses.

公开(公告)号：US11894081B2

公开(公告)日：2024-02-06

申请号：US17685113

申请日：2022-03-02

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Xue Bai Pitner ,  Ken Oowada

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/3495 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26

Abstract: A method for programming a target memory cell of a memory array of a non-volatile memory system, the method comprises determining a total number of erase/programming (EP) cycles that were applied previously to the memory cell and, (1) if the determined total number of cycles does not exceed a threshold value, applying an asymmetric programming scheme, and, (2) if the determined total number of cycles exceeds the threshold value, applying a symmetric programming scheme. Further, a magnitude of a boosting voltage bias (VPASS) that is to be applied to an unselected word line may be determined according to the determined total number of erase/programming (EP) cycles.

公开(公告)号：US20220165341A1

公开(公告)日：2022-05-26

申请号：US17102954

申请日：2020-11-24

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Dengtao Zhao ,  Deepanshu Dutta ,  Ravi Kumar

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30

Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines and are also arranged in strings and configured to retain a threshold voltage within a common range of threshold voltages. A control circuit coupled to the plurality of word lines and the strings is configured to determine an erase upper tail voltage of a distribution of the threshold voltage of the memory cells following an erase operation. The erase upper tail voltage corresponds to a cycling condition of the memory cells. The control circuit is also configured to calculate a program voltage to apply to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells during a program operation based on the erase upper tail voltage.

公开(公告)号：US20230282295A1

公开(公告)日：2023-09-07

申请号：US17685113

申请日：2022-03-02

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Xue Bai Pitner ,  Ken Oowada

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/3495 ,  G11C16/102 ,  G11C16/26 ,  G11C16/08 ,  G11C16/0433

Abstract: A method for programming a target memory cell of a memory array of a non-volatile memory system, the method comprises determining a total number of erase/programming (EP) cycles that were applied previously to the memory cell and, (1) if the determined total number of cycles does not exceed a threshold value, applying an asymmetric programming scheme, and, (2) if the determined total number of cycles exceeds the threshold value, applying a symmetric programming scheme. Further, a magnitude of a boosting voltage bias (VPASS) that is to be applied to an unselected word line may be determined according to the determined total number of erase/programming (EP) cycles.

公开(公告)号：US11749736B2

公开(公告)日：2023-09-05

申请号：US17189153

申请日：2021-03-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xue Bai Pitner ,  Raghuveer S. Makala ,  Fei Zhou ,  Senaka Kanakamedala ,  Ramy Nashed Bassely Said

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/78 ,  H10B41/27 ,  H10B43/27 ,  H10B51/20

CPC classification number: H01L29/42364 ,  H01L29/40111 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/7827 ,  H10B41/27 ,  H10B43/27 ,  H10B51/20

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and memory opening fill structures located in the memory opening and including a vertical semiconductor channel, a dielectric material liner laterally surrounding the vertical semiconductor channel, and a vertical stack of discrete memory elements laterally surrounding the dielectric material liner. A subset of the insulating layers a lower insulating sublayer, an upper insulating sublayer overlying the lower insulating sublayer, and a center insulating sublayer located between and in contact with the lower insulating sublayer and the upper insulating sublayer.

公开(公告)号：US20220165342A1

公开(公告)日：2022-05-26

申请号：US17102657

申请日：2020-11-24

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Deepanshu Dutta ,  Ravi Kumar

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells each connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and the strings determines a program lower tail voltage of a distribution of the threshold voltage following a first program pulse. The control circuit calculates a second program voltage of a second program pulse based on the program lower tail voltage and applies the second program pulse to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells such that the distribution of the threshold voltage of the memory cells have a desired program lower tail voltage without further program pulses.

公开(公告)号：US12027218B2

公开(公告)日：2024-07-02

申请号：US17554321

申请日：2021-12-17

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Prafful Golani ,  Ravi Kumar

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

Abstract: A method for performing a program verify operation with respect to a target memory cell in a memory structure of a non-volatile memory system is provided. The method may include the step of determining a location of the target memory cell within the structure and, based upon the determined location of the target cell and with respect to each programmable memory state: (1) applying a first sense signal at a first point in time, and (2) applying a second sense signal at a second point in time. A time interval between the first and the second points in time is equal to a predetermined optimal time period plus or minus an offset parameter time value.