公开(公告)号：US5972232A

公开(公告)日：1999-10-26

申请号：US984148

申请日：1997-12-03

申请人： Sang Hwan Lee ,  Nam Hwang ,  Min Kyu Song ,  Hee Tae Lee ,  Kwang Eui Pyun

发明人： Sang Hwan Lee ,  Nam Hwang ,  Min Kyu Song ,  Hee Tae Lee ,  Kwang Eui Pyun

IPC分类号： G02B6/35 ,  G02B6/12 ,  G02B6/122 ,  G02B6/42 ,  H01L21/00

CPC分类号： G02B6/122 ,  G02B6/4214 ,  G02B2006/12104 ,  G02B6/4224 ,  G02B6/4232 ,  G02B6/4249

摘要： Disclosed is a micromirror for a hybrid optoelectronic integrated circuit, a method for manufacturing the same, a micromirror-photodetector assembly and an assembly of hybrid optoelectronic integrated circuit for receiving light. The micromirror the present invention comprises a silicon substrate and at least one V-shaped groove formed in the silicon substrate and the V-shaped groove has an inclined surface reflecting light emitted from an optical waveguide to a photodetector. The alignment of the photodetector and the optical fibers is achieved without an additional attachment equipment, by inserting the optical fibers into the V-groove.

摘要翻译： 公开了一种用于混合光电集成电路的微镜，其制造方法，微镜光电检测器组件和用于接收光的混合光电集成电路的组件。 本发明的微反射镜包括硅衬底和形成在硅衬底中的至少一个V形槽，并且V形槽具有将从光波导发射的光反射到光电检测器的倾斜表面。 通过将光纤插入到V形槽中，可以实现光电检测器和光纤的对准而无需额外的附接设备。

公开(公告)号：US06204102B1

公开(公告)日：2001-03-20

申请号：US09207512

申请日：1998-12-09

申请人： Hyung Sup Yoon ,  Jin Hee Lee ,  Byung Sun Park ,  Chul Soon Park ,  Kwang Eui Pyun

发明人： Hyung Sup Yoon ,  Jin Hee Lee ,  Byung Sun Park ,  Chul Soon Park ,  Kwang Eui Pyun

IPC分类号： H01L21338

CPC分类号： B82Y10/00 ,  H01L21/28587 ,  H01L29/66469 ,  H01L29/66878

摘要： A method of forming a gate electrode of a compound semiconductor device includes forming a first insulating film pattern having a first aperture, forming a second insulating film pattern having a second aperture consisting of inverse V-type on the first insulating film pattern, forming a T-type gate electrode by depositing a conductivity film on the entire structure, removing a second insulating film pattern, forming a insulating spacer on a pole sidewall by etching a first insulating film pattern, and forming an ohmic electrode of the source and drain by self-aligning method using T-type gate electrode as a mask. Thereby T-type gate electrode of materials such as refractory metals can be prevented to be deteriorate because of high annealing, as well as it is stably formed, by using an insulating film. Ohmic metal and gate electrodes formed by self-aligning method can be prevented an interconnection by forming an insulating film spacer between these electrodes.

摘要翻译： 一种形成化合物半导体器件的栅电极的方法包括：形成具有第一孔的第一绝缘膜图案，在第一绝缘膜图案上形成具有由反V型构成的第二孔的第二绝缘膜图案，形成T 通过在整个结构上沉积导电膜，去除第二绝缘膜图案，通过蚀刻第一绝缘膜图案在极侧壁上形成绝缘隔离物，并通过自发形成源极和漏极的欧姆电极， 使用T型栅电极作为掩模的对准方法。 因此，通过使用绝缘膜，可以防止诸如难熔金属的材料的T型栅极电极由于高退火而被稳定地形成。 通过自对准方法形成的欧姆金属和栅电极可以通过在这些电极之间形成绝缘膜间隔来防止互连。

公开(公告)号：US6100753A

公开(公告)日：2000-08-08

申请号：US137886

申请日：1998-08-21

申请人： Chang Seok Lee ,  Min Gun Kim ,  Jae Jin Lee ,  Kwang Eui Pyun

发明人： Chang Seok Lee ,  Min Gun Kim ,  Jae Jin Lee ,  Kwang Eui Pyun

IPC分类号： H01L29/70 ,  G05F3/24 ,  G05F1/10

CPC分类号： G05F3/247 ,  G05F3/245

摘要： The present invention relates to a bias stabilization circuit, specifically to a bias stabilization circuit for minimizing the current variations of amplification transistors caused by variations of device parameters which occur during the manufacturing of high-frequency integrated circuits using field-effect transistors, and caused by variations of supply voltage and temperature. In the present invention, the above problem is solved by configuring a level shifter circuit between the drain node and the gate node of the reference voltage generation transistor. Further, by using a constant current source utilizing a depletion transistor and series feedback resistors as a reference current, this circuit becomes stable against the variations of the device parameters as well as the variations of the temperature and supply voltage.

摘要翻译： 本发明涉及一种偏置稳定电路，特别涉及一种偏置稳定电路，用于使由场效应晶体管制造高频集成电路期间发生的器件参数变化引起的放大晶体管的电流变化最小化，并由 电源电压和温度变化。 在本发明中，通过在基准电压产生晶体管的漏极节点和栅极节点之间配置电平移位电路来解决上述问题。 此外，通过使用利用耗尽晶体管和串联反馈电阻器的恒流源作为参考电流，该电路针对器件参数的变化以及温度和电源电压的变化而变得稳定。

公开(公告)号：US6064265A

公开(公告)日：2000-05-16

申请号：US146529

申请日：1998-09-03

申请人： Kwang Jun Yun ,  Min Kun Kim ,  Chang Seok Lee ,  Jae Jin Lee ,  Kwang Eui Pyun

发明人： Kwang Jun Yun ,  Min Kun Kim ,  Chang Seok Lee ,  Jae Jin Lee ,  Kwang Eui Pyun

IPC分类号： H03F3/193 ,  H03G1/00 ,  H03G3/30 ,  H03G3/10

CPC分类号： H03F3/193 ,  H03G1/007 ,  H03G3/3042 ,  H03F2200/294 ,  H03F2200/318

摘要： The present invention relates to a gain control circuit for a low-noise amplifier. A gain control circuit of a 2-stage low-noise amplifier comprising an input stage noise matching circuit, an intermediate impedance matching circuit, a gain control circuit, and an output stage impedance matching circuit, said gain control circuit including: a feedback circuit connected to a transistor of second stage of the 2-stage low-noise amplifier, said feedback circuit detecting the amplified signal through the first stage and the second stage, and feeding the signal back through a switch circuit; and an attenuation circuit for compensating the harmonics of the input signal.

摘要翻译： 本发明涉及一种用于低噪声放大器的增益控制电路。 一种包括输入级噪声匹配电路，中间阻抗匹配电路，增益控制电路和输出级阻抗匹配电路的2级低噪声放大器的增益控制电路，所述增益控制电路包括：反馈电路， 到2级低噪声放大器的第二级的晶体管，所述反馈电路通过第一级和第二级检测放大的信号，并通过开关电路将信号反馈; 以及用于补偿输入信号的谐波的衰减电路。

公开(公告)号：US5939954A

公开(公告)日：1999-08-17

申请号：US955378

申请日：1997-10-21

申请人： Min Gun Kim ,  Choong Hwan Kim ,  Chang Seok Lee ,  Jae Jin Lee ,  Kwang Eui Pyun

发明人： Min Gun Kim ,  Choong Hwan Kim ,  Chang Seok Lee ,  Jae Jin Lee ,  Kwang Eui Pyun

IPC分类号： H01L23/28 ,  H03H7/38 ,  H01L23/64 ,  H05K7/02

CPC分类号： H03H7/38 ,  H01L2224/45144 ,  H01L2224/48091

摘要： The present invention relates to an equivalent circuit of a package ground terminal paddle which is used to mount a microwave integrated circuit, and more particularly, to an approximate equivalent circuit of the package ground terminal paddle by which the expressions of parasitic components can be easily expanded according to the number of gold wires that are down-bonded to the paddle, by introducing an equivalent circuit structure which takes the impedance component output from each terminal as one common impedance component and grounds the common impedance.

摘要翻译： 本发明涉及一种用于安装微波集成电路的封装接地端子板的等效电路，更具体地说涉及封装接地端子板的近似等效电路，通过该电路可以容易地扩展寄生元件的表达 根据下焊接到焊盘的金线的数量，通过引入等效电路结构，其将来自每个端子的阻抗分量输出作为一个公共阻抗分量并将公共阻抗接地。

公开(公告)号：US6057736A

公开(公告)日：2000-05-02

申请号：US135576

申请日：1998-08-18

申请人： Min Gun Kim ,  Chang Seok Lee ,  Jae Jin Lee ,  Kwang Eui Pyun

发明人： Min Gun Kim ,  Chang Seok Lee ,  Jae Jin Lee ,  Kwang Eui Pyun

IPC分类号： H03G1/00 ,  H03F1/34 ,  H03G3/30

CPC分类号： H03F1/342 ,  H03G1/007 ,  H03F2200/151

摘要： The present invention relates to a gain controlled amplifier, and more particularly, to a gain controlled amplifier using active feedback and variable resistance. It is an object of the present invention to provide a gain controlled amplifier minimizing the gain and the degradation of power characteristics generated when adjusting gain in a variable gain amplifier which receives signals having different power levels, amplifies them in accordance with each power level and outputs output signals in a constant power level. In order to achieve the above object, a gain controlled amplifier in accordance with the present invention comprises an amplifier and an active feedback means for negative feedbacking the output of the amplifier to the input of the amplifier, and further has a feedback amount controller inputting the controlled feedback signal to the amplifier by controlling the feedback amount of said active feedback means.

摘要翻译： 增益控制放大器本发明涉及一种增益控制放大器，更具体地说，涉及一种使用有源反馈和可变电阻的增益控制放大器。 本发明的一个目的是提供一种增益控制放大器，其最大程度地减小在接收具有不同功率电平的信号的可变增益放大器中调节增益时产生的功率特性的增益和劣化，根据每个功率电平放大它们 输出信号处于恒定功率电平。 为了实现上述目的，根据本发明的增益控制放大器包括放大器和用于将放大器的输出负反馈到放大器的输入的有源反馈装置，并且还具有反馈量控制器，其输入 通过控制所述主动反馈装置的反馈量来控制反馈信号到放大器。

公开(公告)号：US5862144A

公开(公告)日：1999-01-19

申请号：US956913

申请日：1997-10-23

申请人： Chang Seok Lee ,  Ingab Hwang ,  Min Gun Kim ,  Jae Jin Lee ,  Kwang Eui Pyun

发明人： Chang Seok Lee ,  Ingab Hwang ,  Min Gun Kim ,  Jae Jin Lee ,  Kwang Eui Pyun

IPC分类号： G01R23/00 ,  G01R27/32 ,  G06F11/00

CPC分类号： G01R27/32

摘要： A method for correcting a high frequency measurement error which can exactly correct the high frequency measurement error even with the use of a standard devices of which characteristic have not been verified by calculating the characteristic impedance of the correction device from the characteristics of an auxiliary measuring device calculated by using a general error correction method, and calculating again the once calculated characteristics of the auxiliary measuring device. The method in accordance with the present invention comprises the steps of modelling an auxiliary measuring device used for measuring a high frequency charateristics of the device under test by two transmission lines connected in series between two terminals and a parasitic component connected in parallel between a junction of the two transmission lines and a ground; and moving a reference measurement point to the junction of the two transmission lines by using a phase angle of each transmission line and calculating a reference impedance at the terminal of the auxiliary measuring device to which an object to be measured is connected by using the difference of the resultant reflection coefficients of each port.

摘要翻译： 一种用于校正高频测量误差的方法，即使使用通过从辅助测量装置的特性计算校正装置的特性阻抗尚未验证其特性的标准装置，也可以精确地校正高频测量误差 通过使用通用误差校正方法计算，并再次计算辅助测量装置的一次计算的特性。 根据本发明的方法包括以下步骤：对用于测量被测器件的高频特性的两个传输线串联连接在两个端子之间的辅助测量装置和在两个端子之间并联连接的寄生元件进行建模， 两条传输线和一条地面; 并且通过使用每个传输线的相位角将参考测量点移动到两个传输线的结点，并且通过使用所述差异来计算被测量对象的辅助测量装置的端子处的基准阻抗 每个端口的反射系数。

公开(公告)号：US06614086B2

公开(公告)日：2003-09-02

申请号：US09927312

申请日：2001-08-13

申请人： Gyung Ock Kim ,  In Kyu Kim ,  Kwang Eui Pyun

发明人： Gyung Ock Kim ,  In Kyu Kim ,  Kwang Eui Pyun

IPC分类号： H01L31107

CPC分类号： B82Y20/00 ,  H01L27/15 ,  H01L31/02165 ,  H01L31/035236 ,  H01L31/107

摘要： There is disclosed a photodetector having two or more avalanche-gain layered structures and multi-terminals. The avalanche photodetector includes an emitter light absorption layer structure located between a collector layer and an emitter layer (top contact layer) stacked on a substrate. The photodetector further comprises multiple avalanche-gain layered structures consisting of a charge layer, a multiplication layer and a contact layer between the light absorption layer and said collector layer.

公开(公告)号：US06392781B1

公开(公告)日：2002-05-21

申请号：US09498610

申请日：2000-02-04

申请人： Je Ha Kim ,  Chan Yong Park ,  Kwang Eui Pyun

发明人： Je Ha Kim ,  Chan Yong Park ,  Kwang Eui Pyun

IPC分类号： G02F103

CPC分类号： B82Y20/00 ,  G02F1/01708

摘要： The present invention relates to an electrical field absorbing semiconductor optical modulator, more particularly, to a high speed semiconductor optical modulator and a fabricating method thereof. The present invention includes a high speed semiconductor optical modulator, the optical modulator formed by stacking an n-type light-wave guiding layer, a light absorbing layer, a p-type light-wave guiding layer, a p-type clad layer, and a p-type ohmic contact layer on a substrate successively, the optical modulator having a ridge structure wherein the optical modulator is an electric-field absorbing type, and wherein width W3 of the light absorbing layer is less than the width W1 of the p-type ohmic contact layer. Accordingly, the present invention enables to provide high speed optical modulation of tens of giga rate of which modulating characteristics are excellent by reducing contact resistance and capacitance, which are the major problems of ruining the characteristics of an optical modulator, simultaneously.

摘要翻译： 本发明涉及一种电场吸收半导体光调制器，更具体地涉及一种高速半导体光调制器及其制造方法。 本发明包括高速半导体光调制器，通过堆叠n型光波导层，光吸收层，p型光波导层，p型覆层和 基板上的p型欧姆接触层，其光调制器具有脊结构，其中光调制器是电场吸收型，并且其中光吸收层的宽度W3小于p型欧姆接触层的宽度W1， 型欧姆接触层。 因此，本发明能够通过降低接触电阻和电容来提供几十兆比特的高速光调制，其中调制特性同时是破坏光调制器特性的主要问题。

公开(公告)号：US5989961A

公开(公告)日：1999-11-23

申请号：US116904

申请日：1998-07-17

申请人： Jeon Wook Yang ,  Jae Kyoung Mun ,  Eung Gie Oh ,  Jae Jin Lee ,  Kwang Eui Pyun

发明人： Jeon Wook Yang ,  Jae Kyoung Mun ,  Eung Gie Oh ,  Jae Jin Lee ,  Kwang Eui Pyun

IPC分类号： H01L29/78 ,  H01L21/338 ,  H01L29/812 ,  H01L21/336

CPC分类号： H01L29/66856 ,  H01L29/812

摘要： Disclosed is a method for manufacturing a vertical channel transistor comprising the steps of: selectively implanting a dopant of high concentration into a semiconductor substrate to form a source region; firstly etching the semiconductor substrate using an insulator and a first photoresist pattern as a mask; secondly etching the substrate using a second photoresist pattern having a shape corresponding to said source region as a mask; implanting a dopant of low concentration into the exposed substrate using said second photoresist pattern as a mask to form a vertical channel layer; implanting a dopant of high concentration into the exposed substrate using same mask to form a drain region; activating said dopants, and forming an ohmic contact layer on said drain region; thirdly etching using a third photoresist pattern for exposing the firstly etched portion of the substrate as a mask; depositing a gate metal on the substrate exposed by the thirdly etching; and wiring a metal, respectively. This invention can be easily manufactured a vertical channel transistor having a low parasitic resistance and an extremely small gate length without sophicated complex processes.

摘要翻译： 公开了用于制造垂直沟道晶体管的方法，包括以下步骤：选择性地将高浓度的掺杂剂注入到半导体衬底中以形成源极区; 首先使用绝缘体和第一光致抗蚀剂图案作为掩模蚀刻半导体衬底; 其次使用具有对应于所述源区域的形状的第二光致抗蚀剂图案作为掩模蚀刻所述基板; 使用所述第二光致抗蚀剂图案作为掩模将低浓度的掺杂剂注入暴露的衬底中以形成垂直沟道层; 使用相同的掩模将高浓度的掺杂剂注入暴露的衬底中以形成漏区; 激活所述掺杂剂，并在所述漏极区上形成欧姆接触层; 第三次使用第三光致抗蚀剂图案进行蚀刻，以将基板的第一蚀刻部分暴露为掩模; 在通过第三次蚀刻暴露的衬底上沉积栅极金属; 并分别接线金属。 本发明可以容易地制造具有低寄生电阻和非常小的栅极长度的垂直沟道晶体管，而无需复杂的复杂工艺。