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    GaAs power semiconductor device operating at a low voltage and method for fabricating the same
    2.
    发明授权
    GaAs power semiconductor device operating at a low voltage and method for fabricating the same 失效
    GaAs功率半导体器件以低电压工作及其制造方法

    公开(公告)号：US5760418A

    公开(公告)日：1998-06-02

    申请号：US816805

    申请日：1997-03-19

    申请人： Jong-Lam Lee ,  Hae-Cheon Kim ,  Jae-Kyoung Mun ,  Hyung-Moo Park

    发明人： Jong-Lam Lee ,  Hae-Cheon Kim ,  Jae-Kyoung Mun ,  Hyung-Moo Park

    IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L21/76 ,  H01L21/8252 ,  H01L29/10 ,  H01L29/45 ,  H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072

    CPC分类号： H01L21/7605 ,  H01L21/8252 ,  H01L29/1029 ,  H01L29/1075 ,  H01L29/452 ,  H01L29/66863 ,  H01L29/8128 ,  Y10S977/888 ,  Y10S977/89

    摘要： Disclosed is a GaAs power semiconductor device operating at a low voltage and a method for fabricating the device, the method comprising the steps of sequentially forming a first undoped GaAs buffer layer, a superlattice layer, a second undoped GaAs buffer layer, a channel layer and a surface passivation layer on a semi-insulating GaAs substrate; etching a plurality of layers formed on the substrate using a device isolating mask so as to electrically isolate elements; selectively etching the surface passivation layer to form contact holes for source/drain formation and forming ohmic metallic layers in the contact holes; sequentially removing the surface passivation layer and the channel layer to some deep extent to form a contact hole for gate formation between the source and the drain; forming a gate in the contact hole and at the same time forming source and drain electrodes on the ohmic metallic layers; depositing a first SiN layer over the gate, the source and drain electrodes and the surface passivation layer; selectively etching the first SiN layer so as to expose top surfaces only of the source and drain electrodes; plating a gold layer only on the source and drain electrodes; depositing a second SiN layer over the first SiN layer and the gold layer; and forming a gold coating layer on a rear surface of the substrate. In the device, parasitic carriers in interface between the substrate and the first undoped GaAs buffer layer can be prevented from being introduced into the channel layer by the superlattice layer during operation of the device.

    摘要翻译： 公开了以低电压工作的GaAs功率半导体器件及其制造方法，该方法包括以下步骤：顺序地形成第一未掺杂的GaAs缓冲层，超晶格层，第二未掺杂的GaAs缓冲层，沟道层和 半绝缘GaAs衬底上的表面钝化层; 使用器件隔离掩模蚀刻在衬底上形成的多个层，以便电隔离元件; 选择性地蚀刻表面钝化层以形成用于源极/漏极形成的接触孔并在接触孔中形成欧姆金属层; 顺序地将表面钝化层和沟道层去除一定程度以形成用于在源极和漏极之间形成栅极的接触孔; 在接触孔中形成栅极，同时在欧姆金属层上形成源极和漏极; 在栅极上沉积第一SiN层，源极和漏极以及表面钝化层; 选择性地蚀刻第一SiN层以暴露仅源电极和漏电极的顶表面; 仅在源极和漏极上镀金层; 在第一SiN层和金层上沉积第二SiN层; 以及在所述基板的后表面上形成金涂层。 在该器件中，可以防止衬底与第一未掺杂的GaAs缓冲层之间的界面中的寄生载流子在器件工作期间被超晶格层引入沟道层。

    Method of making a gaAs power semiconductor device operating at a low voltage
    3.
    发明授权
    Method of making a gaAs power semiconductor device operating at a low voltage 失效
    制造在低电压下工作的GaAs功率半导体器件的方法

    公开(公告)号：US5639677A

    公开(公告)日：1997-06-17

    申请号：US665868

    申请日：1996-06-19

    申请人： Jong-Lam Lee ,  Hae-Cheon Kim ,  Jae-Kyoung Mun ,  Hyung-Moo Park

    发明人： Jong-Lam Lee ,  Hae-Cheon Kim ,  Jae-Kyoung Mun ,  Hyung-Moo Park

    IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L21/76 ,  H01L21/8252 ,  H01L29/10 ,  H01L29/45

    CPC分类号： H01L21/7605 ,  H01L21/8252 ,  H01L29/1029 ,  H01L29/1075 ,  H01L29/452 ,  H01L29/66863 ,  H01L29/8128 ,  Y10S977/888 ,  Y10S977/89

    摘要： Disclosed is a GaAs power semiconductor device operating at a low voltage and a method for fabricating the device, the method comprising the steps of sequentially forming a first undoped GaAs buffer layer, a superlattice layer, a second undoped GaAs buffer layer, a channel layer and a surface passivation layer on a semi-insulating GaAs substrate; etching a plurality of layers formed on the substrate using a device isolating mask so as to electrically isolate elements; selectively etching the surface passivation layer to form contact holes for source/drain formation and forming ohmic metallic layers in the contact holes; sequentially removing the surface passivation layer and the channel layer to some deep extent to form a contact hole for gate formation between the source and the drain; forming a gate in the contact hole and at the same time forming source and drain electrodes on the ohmic metallic layers; depositing a first SiN layer over the gate, the source and drain electrodes and the surface passivation layer; selectively etching the first SiN layer so as to expose top surfaces only of the source and drain electrodes; plating a gold layer only on the source and drain electrodes; depositing a second SiN layer over the first SiN layer and the gold layer; and forming a gold coating layer on a rear surface of the substrate. In the device, parasitic carriers in interface between the substrate and the first undoped GaAs buffer layer can be prevented from being introduced into the channel layer by the superlattice layer during operation of the device.

    摘要翻译： 公开了以低电压工作的GaAs功率半导体器件及其制造方法，该方法包括以下步骤：顺序地形成第一未掺杂的GaAs缓冲层，超晶格层，第二未掺杂的GaAs缓冲层，沟道层和 半绝缘GaAs衬底上的表面钝化层; 使用器件隔离掩模蚀刻在衬底上形成的多个层，以便电隔离元件; 选择性地蚀刻表面钝化层以形成用于源极/漏极形成的接触孔并在接触孔中形成欧姆金属层; 顺序地将表面钝化层和沟道层去除一定程度以形成用于在源极和漏极之间形成栅极的接触孔; 在接触孔中形成栅极，同时在欧姆金属层上形成源极和漏极; 在栅极上沉积第一SiN层，源极和漏极以及表面钝化层; 选择性地蚀刻第一SiN层以暴露仅源电极和漏电极的顶表面; 仅在源极和漏极上镀金层; 在第一SiN层和金层上沉积第二SiN层; 以及在所述基板的后表面上形成金涂层。 在该器件中，可以防止衬底与第一未掺杂的GaAs缓冲层之间的界面中的寄生载流子在器件工作期间被超晶格层引入沟道层。