公开(公告)号：US20080090352A1

公开(公告)日：2008-04-17

申请号：US11653362

申请日：2007-01-16

申请人： Sang-Kyoung Lee ,  Jin-Hong Kim ,  Dong-Hwan Kim ,  Won-Sik Shin ,  Woong Lee

发明人： Sang-Kyoung Lee ,  Jin-Hong Kim ,  Dong-Hwan Kim ,  Won-Sik Shin ,  Woong Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336 ,  H01L29/4925

摘要： A method of manufacturing a nonvolatile memory device includes forming a plurality of device isolation regions in a semiconductor substrate, forming a tunneling insulation layer on the semiconductor substrate, forming a first preliminary polysilicon layer in communication with the tunneling insulation layer and the device isolation regions, forming a preliminary amorphous silicon layer on the first preliminary silicon layer, forming a second preliminary polysilicon layer on the preliminary amorphous silicon layer, and patterning the second preliminary polysilicon layer, the preliminary amorphous silicon layer, and the first preliminary polysilicon layer to form a floating gate layer.

摘要翻译： 一种制造非易失性存储器件的方法包括在半导体衬底中形成多个器件隔离区域，在半导体衬底上形成隧道绝缘层，形成与隧道绝缘层和器件隔离区域连通的第一初步多晶硅层， 在所述第一初步硅层上形成初步非晶硅层，在所述初步非晶硅层上形成第二初步多晶硅层，以及构图所述第二初步多晶硅层，所述初步非晶硅层和所述第一初步多晶硅层，以形成浮 门层

公开(公告)号：US07579237B2

公开(公告)日：2009-08-25

申请号：US11653362

申请日：2007-01-16

申请人： Sang-Kyoung Lee ,  Jin-Hong Kim ,  Dong-Hwan Kim ,  Won-Sik Shin ,  Woong Lee

发明人： Sang-Kyoung Lee ,  Jin-Hong Kim ,  Dong-Hwan Kim ,  Won-Sik Shin ,  Woong Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42336 ,  H01L29/4925

摘要： A method of manufacturing a nonvolatile memory device includes forming a plurality of device isolation regions in a semiconductor substrate, forming a tunneling insulation layer on the semiconductor substrate, forming a first preliminary polysilicon layer in communication with the tunneling insulation layer and the device isolation regions, forming a preliminary amorphous silicon layer on the first preliminary silicon layer, forming a second preliminary polysilicon layer on the preliminary amorphous silicon layer, and patterning the second preliminary polysilicon layer, the preliminary amorphous silicon layer, and the first preliminary polysilicon layer to form a floating gate layer.

摘要翻译： 一种制造非易失性存储器件的方法包括在半导体衬底中形成多个器件隔离区域，在半导体衬底上形成隧道绝缘层，形成与隧道绝缘层和器件隔离区域连通的第一初步多晶硅层， 在所述第一初步硅层上形成初步非晶硅层，在所述初步非晶硅层上形成第二初步多晶硅层，以及构图所述第二初步多晶硅层，所述初步非晶硅层和所述第一初步多晶硅层，以形成浮 门层

公开(公告)号：US07492141B2

公开(公告)日：2009-02-17

申请号：US11784162

申请日：2007-04-04

申请人： Jong-Tae Hwang ,  Moon-Sang Jung ,  Dong-Hwan Kim ,  Jin-Sung Kim

发明人： Jong-Tae Hwang ,  Moon-Sang Jung ,  Dong-Hwan Kim ,  Jin-Sung Kim

IPC分类号： G05F1/40 ,  G05F1/56

CPC分类号： H02M3/3376 ,  H02M2001/0058 ,  Y02B70/1433 ,  Y02B70/1491

摘要： A resonant inverter includes a first driver and a second driver for driving a first and second switching devices, respectively, a dead time generator for generating a first drive signal and a second drive signal respectively, a current-controlled oscillator for supplying, to the dead time generator, an output clock having a frequency determined based on a first current input to the current-controlled oscillator, and a current mirror for supplying the first current to the current-controlled oscillator in an amount proportional to a second current flowing through an external resistor. The current mirror includes a track/hold circuit, to supply the second current in an amount equal to an amount of the second current supplied before a variation in the amount of the second current, during a transition of an output signal between the first and second switching devices.

摘要翻译： 谐振逆变器包括分别用于驱动第一和第二开关装置的第一驱动器和第二驱动器，分别用于产生第一驱动信号和第二驱动信号的死区时间发生器，用于向死人提供电流控制振荡器 时间发生器，具有基于对电流控制振荡器的第一电流输入而确定的频率的输出时钟以及用于以与流过外部电流的第二电流成比例的量向电流控制振荡器提供第一电流的电流镜 电阻。 电流镜包括跟踪/保持电路，以在第一和第二电平之间的输出信号的转变期间提供等于第二电流量的变化之前提供的第二电流的量的量的第二电流 开关器件。

公开(公告)号：US20070296462A1

公开(公告)日：2007-12-27

申请号：US11800198

申请日：2007-05-04

申请人： Jong-Tae Hwang ,  Moon-Sang Jung ,  Jin-Sung Kim ,  Dong-Hwan Kim

发明人： Jong-Tae Hwang ,  Moon-Sang Jung ,  Jin-Sung Kim ,  Dong-Hwan Kim

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521

摘要： A logic circuit for high-side gate driver includes a p-MOSFET array connected to a first voltage source, an n-MOSFET array connected to a second voltage source, and a resistor arranged between the p-MOSFET array and the n-MOSFET array, wherein a first node between the resistor and at least one of the p-MOSFETs in the p-MOSFET array is connected to a first output terminal, and a second node between the resistor and at least one of the n-MOSFETs in the n-MOSFET array is connected to a second output terminal. An additional logic circuit can include a second p-MOSFET array, a second n-MOSFET array, and a second resistor between the second p-MOSFET array and the second n-MOSFET array, where an output signal from an output terminal between the first resistor and the first n-MOSFET array is fed back to the second p-MOSFET array and the second n-MOSFET array, and an output signal from an output terminal between the second resistor and the second n-MOSFET array is fed back to the first p-MOSFET array and the first n-MOSFET array.

摘要翻译： 用于高侧栅极驱动器的逻辑电路包括连接到第一电压源的p-MOSFET阵列，连接到第二电压源的n-MOSFET阵列和布置在p-MOSFET阵列和n-MOSFET阵列之间的电阻器 ，其中所述电阻器和所述p-MOSFET阵列中的至少一个p-MOSFET之间的第一节点连接到第一输出端子，并且所述电阻器和所述n个中的至少一个n-MOSFET的第二节点 -MOSFET阵列连接到第二输出端。 附加的逻辑电路可以包括第二p-MOSFET阵列，第二n-MOSFET阵列和在第二p-MOSFET阵列和第二n-MOSFET阵列之间的第二电阻，其中来自第一 电阻器和第一n-MOSFET阵列被反馈到第二p-MOSFET阵列和第二n-MOSFET阵列，并且来自第二电阻器和第二n-MOSFET阵列之间的输出端的输出信号被反馈到 第一个p-MOSFET阵列和第一个n-MOSFET阵列。

公开(公告)号：US20070103220A1

公开(公告)日：2007-05-10

申请号：US11479290

申请日：2006-06-29

申请人： Dong-Hwan Kim ,  Si-Nae Kim ,  Kae-Dal Kwack ,  Jae-Jin Lee

发明人： Dong-Hwan Kim ,  Si-Nae Kim ,  Kae-Dal Kwack ,  Jae-Jin Lee

IPC分类号： G06F1/04

CPC分类号： G06F1/10

摘要： A clock driver is provided. A first driving unit is configured with a plurality of drivers and receives a first clock signal to drive a first pumping clock. A second driving unit is configured with a plurality of drivers and receives a second clock signal to drive a second pumping clock. A charge recycling switch is connected between an output terminal of the first driving unit and an output terminal of the second driving unit. A switch controller selectively transfers an input clock signal of the first or second driving unit to the charge recycling switch in response to the first and second pumping clock signals.

摘要翻译： 提供时钟驱动程序。 第一驱动单元配置有多个驱动器并且接收第一时钟信号以驱动第一泵送时钟。 第二驱动单元配置有多个驱动器并且接收第二时钟信号以驱动第二抽时钟。 电荷循环开关连接在第一驱动单元的输出端和第二驱动单元的输出端之间。 开关控制器响应于第一和第二抽吸时钟信号选择性地将第一或第二驱动单元的输入时钟信号传送到电荷再循环开关。

公开(公告)号：US20070046884A1

公开(公告)日：2007-03-01

申请号：US11510145

申请日：2006-08-22

申请人： Bo-Young An ,  Hyung-Guel Kim ,  Dong-Hwan Kim ,  Do-Kyun Kim

发明人： Bo-Young An ,  Hyung-Guel Kim ,  Dong-Hwan Kim ,  Do-Kyun Kim

IPC分类号： G02F1/1345

CPC分类号： G02F1/13454 ,  G02F1/1345 ,  G02F2001/133391

摘要： A reduced power thin-film transistor (TFT) array substrate includes a display section, a peripheral section, a driving circuit section and a driver chip. The display section includes a high definition section and a low definition section. The peripheral section surrounds the display section. The driving circuit section is formed on the peripheral section and is configured to provide the high definition section with a plurality of first gate signals. The driver chip is mounted on the peripheral section to provide the low definition section with a plurality of second gate signals.

摘要翻译： 降低功率薄膜晶体管（TFT）阵列基板包括显示部分，周边部分，驱动电路部分和驱动器芯片。 显示部分包括高清晰度部分和低分辨率部分。 外围部分围绕显示部分。 所述驱动电路部分形成在所述外围部分上并且被配置为向所述高清晰度部分提供多个第一栅极信号。 驱动器芯片安装在外围部分上，以提供具有多个第二栅极信号的低清晰度部分。

公开(公告)号：US20060160387A1

公开(公告)日：2006-07-20

申请号：US11323375

申请日：2005-12-29

申请人： Sok-San Kim ,  Dong-Hwan Kim ,  Joong-Ha Ahn ,  Jae-Gyoung Kim

发明人： Sok-San Kim ,  Dong-Hwan Kim ,  Joong-Ha Ahn ,  Jae-Gyoung Kim

IPC分类号： H01R13/62

CPC分类号： H05K5/02

摘要： A display device which has a simplified assembly process and minimized product damage. The display device includes a display panel; a chassis base having a first surface for supporting and for fixing the display panel thereto; a circuit board fixed to a second surface of the chassis base, the circuit board having circuit elements for driving the display panel; and at least one main fastening unit for fixing the circuit board to the chassis base such that a gap is formed between the circuit board and the chassis base. The main fastening unit includes a main body, fasteners, and first and second protrusions to form engaged portions. The display device may be a plasma display device.

摘要翻译： 一种显示装置，其具有简化的组装过程并最小化产品损坏。 显示装置包括显示面板; 具有用于支撑显示面板并固定显示面板的第一表面的底架; 电路板，其固定到所述底座的第二表面，所述电路板具有用于驱动所述显示面板的电路元件; 以及用于将电路板固定到底座的至少一个主紧固单元，使得在电路板和底座之间形成间隙。 主紧固单元包括主体，紧固件，以及形成接合部分的第一和第二突起。 显示装置可以是等离子体显示装置。

公开(公告)号：US07042289B2

公开(公告)日：2006-05-09

申请号：US10817705

申请日：2004-04-02

申请人： Jong-Tae Hwang ,  Dong-Hwan Kim ,  Yun-Kee Lee

发明人： Jong-Tae Hwang ,  Dong-Hwan Kim ,  Yun-Kee Lee

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F2203/45366

摘要： A transconductance control circuit of a rail-to-rail differential input stage is described. The transconductance control circuit senses the gate-source voltages of PMOS and NMOS differential pairs, converts the sensed voltage to a current, compares the current with a reference current, and controls the currents of the PMOS and NMOS differential pairs to control the transconductance of the RTR differential input stage. Also, various types of biasing techniques and matching techniques are used to reduce the variations of the transconductance.

摘要翻译： 描述了轨到轨差分输入级的跨导控制电路。 跨导控制电路检测PMOS和NMOS差分对的栅极 - 源极电压，将感测到的电压转换为电流，将电流与参考电流进行比较，并控制PMOS和NMOS差分对的电流，以控制 RTR差分输入级。 此外，使用各种类型的偏置技术和匹配技术来减少跨导的变化。

公开(公告)号：US20060055655A1

公开(公告)日：2006-03-16

申请号：US11225294

申请日：2005-09-13

申请人： Dong-Wan Choi ,  Dong-Hwan Kim ,  Byung-Chang Shim

发明人： Dong-Wan Choi ,  Dong-Hwan Kim ,  Byung-Chang Shim

IPC分类号： G09G3/36

CPC分类号： G09G3/3655 ,  G09G3/3688 ,  G09G2310/0221 ,  G09G2330/04

摘要： In a driving unit and a display apparatus, a master driving chip includes a common voltage generator configured to receive power and generate a master common voltage and a slave common voltage and a first data driver configured to output a master image signal based on the master common voltage and a master data signal. A slave driving chip includes a second data driver configured to output a slave image signal based on the slave common voltage from the common voltage generator and a slave data signal. Accordingly, the malfunction of the driving unit and the display apparatus may be prevented.

摘要翻译： 在驱动单元和显示装置中，主驱动芯片包括被配置为接收电力并产生主公共电压和从公共电压的公共电压发生器，以及配置为基于主公共端输出主映像信号的第一数据驱动器 电压和主数据信号。 从驱动芯片包括第二数据驱动器，其配置为基于来自公共电压发生器的从公共电压和从属数据信号输出从属图像信号。 因此，可以防止驱动单元和显示装置的故障。

公开(公告)号：US20050174054A1

公开(公告)日：2005-08-11

申请号：US11052192

申请日：2005-02-08

申请人： Tae-Kyoung Kang ,  Sok-San Kim ,  Dong-Hwan Kim ,  In-Soo Cho ,  Joong-Ha Ahn

发明人： Tae-Kyoung Kang ,  Sok-San Kim ,  Dong-Hwan Kim ,  In-Soo Cho ,  Joong-Ha Ahn

IPC分类号： G09F9/00 ,  H01J17/28 ,  H01J17/49 ,  H05K7/20

CPC分类号： H05K7/20963

摘要： A chassis assembly to reduce a discharge delay in a plasma display apparatus and a plasma display apparatus having the same. The chassis assembly includes a chassis having a thermal conductivity in a range of about 10 W/mK to about 100 W/mK.

摘要翻译： 一种用于减小等离子体显示装置中的放电延迟的底架组件和具有该放电延迟的等离子体显示装置。 底盘组件包括具有约10W / mK至约100W / mK范围内的热导率的底盘。