公开(公告)号：US20110069568A1

公开(公告)日：2011-03-24

申请号：US12952328

申请日：2010-11-23

申请人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

发明人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

IPC分类号： G11C7/08 ,  G11C7/12 ,  G11C7/22

CPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C2207/005 ,  G11C2207/065

摘要： A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.

摘要翻译： 半导体存储器件包括多个存储单元阵列块，位线读出放大器，可被控制为导通或截止的本地读出放大器，数据读出放大器和控制器。 控制器响应于第一和第二信号激活预定持续时间的局部感测控制信号。 第一信号是激活位线读出放大器的位线检测使能信号，并且在位线检测使能信号被激活之后局部读出放大器被激活预定的持续时间。 第二信号与连接一对位线和一对本地输入/输出线的列选择线信号同相激活或去激活。 因此，可以根据操作条件接通或关闭本地读出放大器，由此增加tRCD参数并减少电流消耗。 可以通过组合本地读出放大器与在读取操作期间不需要预充电和均衡的电流型数据读出放大器来提高半导体存储器件的工作速度。

公开(公告)号：US07855926B2

公开(公告)日：2010-12-21

申请号：US11188184

申请日：2005-07-20

申请人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

发明人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

IPC分类号： G11C7/00 ,  G11C7/02

CPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C2207/005 ,  G11C2207/065

摘要： A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.

摘要翻译： 半导体存储器件包括多个存储单元阵列块，位线读出放大器，可被控制为导通或截止的本地读出放大器，数据读出放大器和控制器。 控制器响应于第一和第二信号激活预定持续时间的局部感测控制信号。 第一信号是激活位线读出放大器的位线检测使能信号，并且在位线检测使能信号被激活之后局部读出放大器被激活预定的持续时间。 第二信号与连接一对位线和一对本地输入/输出线的列选择线信号同相激活或去激活。 因此，可以根据操作条件接通或关闭本地读出放大器，由此增加tRCD参数并减少电流消耗。 可以通过组合本地读出放大器与在读取操作期间不需要预充电和均衡的电流型数据读出放大器来提高半导体存储器件的工作速度。

公开(公告)号：US20060028888A1

公开(公告)日：2006-02-09

申请号：US11188184

申请日：2005-07-20

申请人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

发明人： Sang-Woong Shin ,  Chul-Soo Kim ,  Young-Hyun Jun ,  Sang-Bo Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C2207/005 ,  G11C2207/065

摘要： A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.

摘要翻译： 半导体存储器件包括多个存储单元阵列块，位线读出放大器，可被控制为导通或截止的本地读出放大器，数据读出放大器和控制器。 控制器响应于第一和第二信号激活预定持续时间的局部感测控制信号。 第一信号是激活位线读出放大器的位线检测使能信号，并且在位线检测使能信号被激活之后局部读出放大器被激活预定的持续时间。 第二信号与连接一对位线和一对本地输入/输出线的列选择线信号同相激活或去激活。 因此，可以根据操作条件接通或关闭本地读出放大器，由此增加tRCD参数并减少电流消耗。 可以通过组合本地读出放大器与在读取操作期间不需要预充电和均衡的电流型数据读出放大器来提高半导体存储器件的工作速度。

公开(公告)号：US07366822B2

公开(公告)日：2008-04-29

申请号：US10840268

申请日：2004-05-07

申请人： Jin-Seok Kwak ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Sang-Bo Lee ,  Min-Sang Park ,  Chul-Soo Kim

发明人： Jin-Seok Kwak ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Sang-Bo Lee ,  Min-Sang Park ,  Chul-Soo Kim

IPC分类号： G06F12/00 ,  G11C8/00

CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C11/4082 ,  G11C11/4087

摘要： A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are possible. The semiconductor memory device may include an address bank buffer, address buffer, column predecoder and/or a decoder. The semiconductor memory device may begin execution of a write command in a bank in one clock cycle and begin execution of a read command in the following clock cycle, therefore, bus efficiency is increased and/or write-to-read turn around time is reduced.

摘要翻译： 半导体存储器件包括多个存储体。 数据路径可以被划分为读取数据路径和写入数据路径，因此并行处理写入和读取命令是可能的。 半导体存储器件可以包括地址库缓冲器，地址缓冲器，列预解码器和/或解码器。 半导体存储器件可以在一个时钟周期内开始执行存储体中的写入命令，并且在随后的时钟周期开始执行读取命令，因此总线效率增加和/或写入读取时间减少 。

公开(公告)号：US06603687B2

公开(公告)日：2003-08-05

申请号：US10074592

申请日：2002-02-11

申请人： Young-Hyun Jun ,  Chul-Soo Kim ,  Ho-Young Song

发明人： Young-Hyun Jun ,  Chul-Soo Kim ,  Ho-Young Song

IPC分类号： G11C700

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222

摘要： Devices, circuits and methods synchronize the inputting and outputting of groups of data into a memory cell array and out of a device. Synchronizing is performed by internal clock signals, both of which are derived from a single delay feedback loop.

摘要翻译： 设备，电路和方法将数据组的输入和输出同步到存储单元阵列中并从设备中输出。 通过内部时钟信号执行同步，两者都是从单个延迟反馈回路得出的。

公开(公告)号：US07242232B2

公开(公告)日：2007-07-10

申请号：US11126428

申请日：2005-05-10

申请人： Chul-Soo Kim ,  Byung-Hoon Jeong

发明人： Chul-Soo Kim ,  Byung-Hoon Jeong

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222

摘要： We describe and claim an internal signal replication device and method. A circuit comprising a selector to select one of a plurality of internally generated clock signals, and a compensation circuit to replicate the selected clock signal from a reference clock signal.

摘要翻译： 我们描述并声明内部信号复制设备和方法。 一种电路，包括选择器以选择多个内部产生的时钟信号中的一个，以及补偿电路，以从参考时钟信号复制所选择的时钟信号。

公开(公告)号：US06323664B1

公开(公告)日：2001-11-27

申请号：US09620018

申请日：2000-07-20

申请人： Sung-Hoon Kim ,  Chul-Soo Kim

发明人： Sung-Hoon Kim ,  Chul-Soo Kim

IPC分类号： G01R3102

CPC分类号： G11C29/48 ,  G11C29/006

摘要： Disclosed herein is a semiconductor memory device that includes a memory cell array and a plurality of pads for providing data to and from the memory cell array. A plurality of input/output line pairs corresponds to the plurality of pads. A reading means reads out the data from the memory cell array through the plurality of input/output line pairs and pads. A switch control circuit generates sequential switch control signals during a test mode. A switch control means receives the data from the reading means during the test mode. The switching means sequentially transfers the data to a representative pad responsive to the switch control signals. The present invention allows testing for defective memory cells at a wafer level using a limited number of probe needles.

摘要翻译： 这里公开了一种半导体存储器件，其包括存储单元阵列和用于向存储单元阵列提供数据的多个焊盘。 多个输入/输出线对对应于多个焊盘。 读取装置通过多个输入/输出线对和焊盘从存储单元阵列中读出数据。 开关控制电路在测试模式期间产生顺序的开关控制信号。 开关控制装置在测试模式期间从读取装置接收数据。 切换装置响应于开关控制信号顺序地将数据传送到代表性焊盘。 本发明允许使用有限数量的探针针对晶片级的缺陷存储单元进行测试。

公开(公告)号：US20080246506A1

公开(公告)日：2008-10-09

申请号：US12059380

申请日：2008-03-31

申请人： Chul-Soo Kim

发明人： Chul-Soo Kim

IPC分类号： G01R31/26

CPC分类号： G01R31/2621

摘要： An apparatus and a method for measuring an effective channel. The apparatus includes an automatic measurement system including a testing terminal for a substrate, a switching matrix disposed at one side of the automatic measurement system, a leakage current measuring device and a capacitance measuring device electrically connected to the switching matrix by a predetermined terminal, and a controller which controls the automatic measurement system, the leakage current measuring device, and the capacitance measuring device.

摘要翻译： 一种用于测量有效信道的装置和方法。 该装置包括：自动测量系统，包括：基板测试端子;设置在自动测量系统一侧的开关矩阵;漏电流测量装置;以及通过预定端子与开关矩阵电连接的电容测量装置;以及 控制自动测量系统的控制器，漏电流测量装置和电容测量装置。

公开(公告)号：US20070047367A1

公开(公告)日：2007-03-01

申请号：US11506878

申请日：2006-08-21

申请人： Doo-Young Kim ,  Soon-Seob Lee ,  Chul-Soo Kim

发明人： Doo-Young Kim ,  Soon-Seob Lee ,  Chul-Soo Kim

IPC分类号： G11C8/00

CPC分类号： G11C8/10

摘要： Semiconductor memory devices, block select decoding circuits and a method of activating a word line are provided. An example semiconductor memory device may include a plurality of memory banks. Each of the plurality of memory banks may include memory blocks which may be arranged in different addressable orders. If two edge memory blocks are activated in a given one of the plurality of memory banks, a non-edge memory block may be concurrently activated in at least one of remaining memory banks other than the given one memory bank. Accordingly, a number of concurrently activated memory blocks, a voltage required to enable a word line and noise may be reduced. The example semiconductor device may include the example block select decoding circuit, and likewise may perform the example method of activating a word line with an activation of a reduced number of memory blocks.

摘要翻译： 提供半导体存储器件，块选择解码电路和激活字线的方法。 示例性半导体存储器件可以包括多个存储体。 多个存储体中的每一个可以包括可以以不同的可寻址顺序排列的存储块。 如果在多个存储体中的给定的一个存储体中激活了两个边缘存储器块，则非边缘存储器块可以在除给定的一个存储体之外的剩余存储体的至少一个中同时激活。 因此，可以减少多个同时激活的存储块，使得字线和噪声所需的电压。 示例性半导体器件可以包括示例块选择解码电路，并且同样可以执行用减少数量的存储器块的激活来激活字线的示例方法。

公开(公告)号：US6072846A

公开(公告)日：2000-06-06

申请号：US896788

申请日：1997-07-18

申请人： Gye-Hyun Kyung ,  Chul-Soo Kim

发明人： Gye-Hyun Kyung ,  Chul-Soo Kim

IPC分类号： H03L7/00 ,  G06F1/10 ,  H03L7/06 ,  H03L7/081 ,  H03L7/089 ,  H03L7/16 ,  H04L7/00 ,  H03K5/13

CPC分类号： H03L7/06 ,  G06F1/10 ,  H03L7/0812 ,  H04L7/0012 ,  H03L7/0891

摘要： A clock supply device for distributing a source clock signal to memory elements in a synchronous memory system reduces skew and improves accuracy by transmitting a first clock signal from a synchronization section located at a first position to a clock distribution section located at a second position and then feeding back a second clock signal to the synchronization section which includes a phase locked loop or delay locked loop. The synchronization section locks the first signal with the source clock signal, thereby controlling the skew between the first clock signal and the source clock signal. The clock distributing section distributes the first clock signal to memory elements and generates the second clock signal as a feedback signal responsive to the first clock signal. The clock supply device includes a first transmission line for transmitting the first clock signal from the first position to the second position, and a second transmission line for transmitting the second clock signal back to the first position. A third transmission line is optionally provided to transmit the source clock signal from a clock generating section located at a third position to the synchronization section at the first position. The signal delay characteristics of the second and third transmission lines are preferably equal.

摘要翻译： 用于将源时钟信号分配到同步存储器系统中的存储器元件的时钟提供装置通过从位于第一位置的同步部分发送第一时钟信号到位于第二位置的时钟分配部分来减少偏差并提高精度，然后 将第二时钟信号反馈到包括锁相环或延迟锁定环的同步部分。 同步部分用源时钟信号锁定第一信号，由此控制第一时钟信号和源时钟信号之间的偏斜。 时钟分配部分将第一时钟信号分配给存储器元件，并响应于第一时钟信号产生第二时钟信号作为反馈信号。 时钟供给装置包括用于将第一时钟信号从第一位置发送到第二位置的第一传输线和用于将第二时钟信号发送回第一位置的第二传输线。 可选地提供第三传输线，以将来自位于第三位置的时钟产生部分的源时钟信号从第一位置发送到同步部分。 第二和第三传输线的信号延迟特性优选相等。