公开(公告)号：US20080086858A1

公开(公告)日：2008-04-17

申请号：US11987844

申请日：2007-12-05

申请人： Sang-Yeop Lee ,  Cheul-Joong Youn

发明人： Sang-Yeop Lee ,  Cheul-Joong Youn

IPC分类号： H01L21/67

CPC分类号： H01L21/67092 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  Y10T29/41

摘要： A method and apparatus of fabricating a semiconductor device by back grinding and dicing is disclosed. The method may include at least adhering a protection tape for back grinding on a front surface of a semiconductor wafer, back grinding a rear surface of the semiconductor wafer while the protection tape faces downward, loading the semiconductor wafer to dicing equipment when the front surface having the protection tape faces downward, detecting a dicing position formed on the front surface of the semiconductor wafer, and dicing the semiconductor wafer with the protection tape adhering thereon into individual semiconductor chips in accordance with the detected dicing position. The dicing equipment may have a transparent aligning part for aligning the semiconductor wafer and a chuck part for supporting the semiconductor wafer.

公开(公告)号：US20050196939A1

公开(公告)日：2005-09-08

申请号：US10984843

申请日：2004-11-10

申请人： Sang-Yeop Lee ,  Cheul-Joong Youn

发明人： Sang-Yeop Lee ,  Cheul-Joong Youn

IPC分类号： H01L21/78 ,  H01L21/301 ,  H01L21/44 ,  H01L21/46 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/67092 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  Y10T29/41

摘要： A method and apparatus of fabricating a semiconductor device by back grinding and dicing is disclosed. The method may include at least adhering a protection tape for back grinding on a front surface of a semiconductor wafer, back grinding a rear surface of the semiconductor wafer while the protection tape faces downward, loading the semiconductor wafer to dicing equipment when the front surface having the protection tape faces downward, detecting a dicing position formed on the front surface of the semiconductor wafer, and dicing the semiconductor wafer with the protection tape adhering thereon into individual semiconductor chips in accordance with the detected dicing position. The dicing equipment may have a transparent aligning part for aligning the semiconductor wafer and a chuck part for supporting the semiconductor wafer.

摘要翻译： 公开了一种通过背面研磨和切割制造半导体器件的方法和装置。 该方法可以包括至少在半导体晶片的前表面上粘贴用于背面研磨的保护带，当保护带朝下时，背面研磨半导体晶片的后表面，当前表面具有 保护带面向下，检测形成在半导体晶片的前表面上的切割位置，并根据检测到的切割位置将其上粘附有保护带的半导体晶片切割成单独的半导体芯片。 切割设备可以具有用于对准半导体晶片的透明对准部分和用于支撑半导体晶片的卡盘部分。

公开(公告)号：US07323397B2

公开(公告)日：2008-01-29

申请号：US10984843

申请日：2004-11-10

申请人： Sang-Yeop Lee ,  Cheul-Joong Youn

发明人： Sang-Yeop Lee ,  Cheul-Joong Youn

IPC分类号： H00L21/46 ,  H00L21/30 ,  H00L21/78 ,  H00L21/50 ,  H00L23/544 ,  H00L21/768

CPC分类号： H01L21/67092 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  Y10T29/41

摘要： A method and apparatus of fabricating a semiconductor device by back grinding and dicing is disclosed. The method may include at least adhering a protection tape for back grinding on a front surface of a semiconductor wafer, back grinding a rear surface of the semiconductor wafer while the protection tape faces downward, loading the semiconductor wafer to dicing equipment when the front surface having the protection tape faces downward, detecting a dicing position formed on the front surface of the semiconductor wafer, and dicing the semiconductor wafer with the protection tape adhering thereon into individual semiconductor chips in accordance with the detected dicing position. The dicing equipment may have a transparent aligning part for aligning the semiconductor wafer and a chuck part for supporting the semiconductor wafer.

摘要翻译： 公开了一种通过背面研磨和切割制造半导体器件的方法和装置。 该方法可以包括至少在半导体晶片的前表面上粘贴用于背面研磨的保护带，当保护带朝下时，背面研磨半导体晶片的后表面，当前表面具有 保护带面向下，检测形成在半导体晶片的前表面上的切割位置，并根据检测到的切割位置将其上粘附有保护带的半导体晶片切割成单独的半导体芯片。 切割设备可以具有用于对准半导体晶片的透明对准部分和用于支撑半导体晶片的卡盘部分。

公开(公告)号：US20050242417A1

公开(公告)日：2005-11-03

申请号：US11001173

申请日：2004-12-02

申请人： Cheul-Joong Youn ,  Sang-Yeop Lee ,  Sang-Hyeop Lee

发明人： Cheul-Joong Youn ,  Sang-Yeop Lee ,  Sang-Hyeop Lee

IPC分类号： H01L21/48 ,  H01L23/495 ,  H01L29/40

CPC分类号： H01L24/27 ,  H01L23/49503 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor chip package may have through holes extending from a chip contact surface of a film type die attaching material to a second surface of a die pad. A resin encapsulant may extend into the through holes to directly contact portions of a semiconductor chip that are superposed over the through holes. The through holes may be formed using a stamping method.

摘要翻译： 半导体芯片封装可以具有从膜型管芯附接材料的芯片接触表面延伸到管芯焊盘的第二表面的通孔。 树脂密封剂可以延伸到通孔中以直接接触覆盖在通孔上的半导体芯片的部分。 可以使用冲压法形成通孔。

公开(公告)号：US20050023659A1

公开(公告)日：2005-02-03

申请号：US10897098

申请日：2004-07-23

申请人： Sang-Yeop Lee ,  Cheul-Joong Youn

发明人： Sang-Yeop Lee ,  Cheul-Joong Youn

IPC分类号： H01L23/12 ,  H01L21/60 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10 ,  H01L25/18 ,  H05K1/02 ,  H05K1/14 ,  H05K3/34 ,  H01L23/02

CPC分类号： H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/023 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/09972 ,  H05K2201/10477 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2201/2036 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor chip package may include functional and packaging parts, which may be separated into first and second areas respectively, and designated only for a specific type of semiconductor material. The first area may be designated only for functional material, while the second area may be designated only for packaging material. The first area may include a semiconductor chip and/or passive elements, while the second area may include packaging material for example, solder and/or contact pads.

摘要翻译： 半导体芯片封装可以包括功能和封装部件，其可分别分成第一和第二区域，并且仅被指定用于特定类型的半导体材料。 第一个区域可以仅用于功能材料，而第二个区域可以仅用于包装材料。 第一区域可以包括半导体芯片和/或无源元件，而第二区域可以包括例如焊料和/或接触焊盘的封装材料。

公开(公告)号：US07495315B2

公开(公告)日：2009-02-24

申请号：US11987844

申请日：2007-12-05

申请人： Sang-Yeop Lee ,  Cheul-Joong Youn

发明人： Sang-Yeop Lee ,  Cheul-Joong Youn

IPC分类号： H01L23/544 ,  H01L21/768 ,  H01L21/78 ,  H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L21/46

CPC分类号： H01L21/67092 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  Y10T29/41

摘要： A method and apparatus of fabricating a semiconductor device by back grinding and dicing is disclosed. The method may include at least adhering a protection tape for back grinding on a front surface of a semiconductor wafer, back grinding a rear surface of the semiconductor wafer while the protection tape faces downward, loading the semiconductor wafer to dicing equipment when the front surface having the protection tape faces downward, detecting a dicing position formed on the front surface of the semiconductor wafer, and dicing the semiconductor wafer with the protection tape adhering thereon into individual semiconductor chips in accordance with the detected dicing position. The dicing equipment may have a transparent aligning part for aligning the semiconductor wafer and a chuck part for supporting the semiconductor wafer.

摘要翻译： 公开了一种通过背面研磨和切割制造半导体器件的方法和装置。 该方法可以包括至少在半导体晶片的前表面上粘贴用于背面研磨的保护带，当保护带朝下时，背面研磨半导体晶片的后表面，当前表面具有 保护带面向下，检测形成在半导体晶片的前表面上的切割位置，并根据检测到的切割位置将其上粘附有保护带的半导体晶片切割成各个半导体芯片。 切割设备可以具有用于对准半导体晶片的透明对准部分和用于支撑半导体晶片的卡盘部分。

公开(公告)号：US20070007634A1

公开(公告)日：2007-01-11

申请号：US11516558

申请日：2006-09-07

申请人： Cheul-Joong Youn ,  Sang-Yeop Lee ,  Sang-Hyeop Lee

发明人： Cheul-Joong Youn ,  Sang-Yeop Lee ,  Sang-Hyeop Lee

IPC分类号： H01L23/495 ,  H01L21/00

CPC分类号： H01L24/27 ,  H01L23/49503 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor chip package may have through holes extending from a chip contact surface of a film type die attaching material to a second surface of a die pad. A resin encapsulant may extend into the through holes to directly contact portions of a semiconductor chip that are superposed over the through holes. The through holes may be formed using a stamping method.

摘要翻译： 半导体芯片封装可以具有从膜型管芯附接材料的芯片接触表面延伸到管芯焊盘的第二表面的通孔。 树脂密封剂可以延伸到通孔中以直接接触覆盖在通孔上的半导体芯片的部分。 可以使用冲压法形成通孔。

公开(公告)号：US08293138B2

公开(公告)日：2012-10-23

申请号：US12004274

申请日：2007-12-19

申请人： Hyoung-Juhn Kim ,  Jeung Woo Lee ,  Tae-Hoon Lim ,  Suk Woo Nam ,  Seong-Ahn Hong ,  In-Hwan Oh ,  Hyung Chul Ham ,  Sang-Yeop Lee

发明人： Hyoung-Juhn Kim ,  Jeung Woo Lee ,  Tae-Hoon Lim ,  Suk Woo Nam ,  Seong-Ahn Hong ,  In-Hwan Oh ,  Hyung Chul Ham ,  Sang-Yeop Lee

IPC分类号： H01B1/12 ,  C08G73/06

CPC分类号： C08J5/2256 ,  C08G73/18 ,  C08J2379/04 ,  H01M8/103 ,  H01M8/1048 ,  H01M8/1072 ,  H01M2300/0082 ,  Y02P70/56

摘要： A partially sulfonated polybenzimidazole based polymer for fuel cell membrane is prepared by copolymerizing monomers of 3,3′-diaminobenzidine, isophthalic acid and 5-sulfoisophthalic acid to obtain a partially sulfonated polybenzimidazole, and doping the partially sulfonated polybenzimidazole with inorganic acid.

摘要翻译： 通过共聚3,3'-二氨基联苯胺，间苯二甲酸和5-磺基间苯二甲酸的单体制备用于燃料电池膜的部分磺化的聚苯并咪唑基聚合物，以获得部分磺化的聚苯并咪唑，并用无机酸掺杂部分磺化的聚苯并咪唑。

公开(公告)号：US20050054186A1

公开(公告)日：2005-03-10

申请号：US10885769

申请日：2004-07-08

申请人： Jin-Ho Kim ,  In-Ku Kang ,  Sang-Yeop Lee

发明人： Jin-Ho Kim ,  In-Ku Kang ,  Sang-Yeop Lee

IPC分类号： H01L21/60 ,  H01L21/44 ,  H01L21/607

CPC分类号： H01L24/85 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85951 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A method of wire bonding, a semiconductor chip, and a semiconductor package provides stitch-stitch bonds of a wire on a bond pad of a chip as well as on a bond position of a substrate. A ball-stitch bump is formed on an end of the wire extending from a capillary or provided on the bond pad of the chip. A ball-stitch bump is formed on the bond pad of the chip by pressing down the ball of the wire on the bond pad. A ball-stitch stitch bond of the wire is formed on the ball-stitch bump by pressing down the wire on the ball-stitch bump. The capillary is moved from the bond pad to the bond position, while loosening the wire. A stitch bond of the wire is formed on the bond position by pressing down the wire on the bond position, and then separated from the wire within the capillary. The method of wire bonding, a semiconductor chip, and a semiconductor package can reduce or minimize a moving path of the capillary and provide more effective wire bonding.

摘要翻译： 引线键合，半导体芯片和半导体封装的方法在芯片的焊盘和基板的接合位置上提供线的针脚结合。 在从毛细管延伸或设置在芯片的接合焊盘上的导线的端部上形成球形针迹。 通过在接合焊盘上压下导线的球，在芯片的接合焊盘上形成球针凸点。 通过按压球形针凸块上的线，在球形针迹上形成线迹的针迹缝合。 毛细管从接合垫移动到接合位置，同时松开电线。 通过在接合位置压下导线，在接合位置形成线的针脚接合，然后与毛细管内的线分离。 引线键合，半导体芯片和半导体封装的方法可以减少或最小化毛细管的移动路径并提供更有效的引线键合。

公开(公告)号：US20050023674A1

公开(公告)日：2005-02-03

申请号：US10632700

申请日：2003-07-31

申请人： In-Ku Kang ,  Hee-Kook Choi ,  Sang-Ho An ,  Sang-Yeop Lee

发明人： In-Ku Kang ,  Hee-Kook Choi ,  Sang-Ho An ,  Sang-Yeop Lee

IPC分类号： H01L25/065 ,  H01L23/34

CPC分类号： H01L24/48 ,  H01L24/45 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Provided herein are multi-chip modules (MCMs) having bonding wires and fabrication methods thereof. The multi-chip module includes a substrate and a plurality of chips sequentially stacked. At least one top chip, stacked above a lowest chip, has an insulating film that covers the backside thereof. Also, each of the stacked chips has bonding pads formed on the periphery or edges of its upper surface. At least one insulator is interposed between the stacked chips. The insulator exposes the pads on the underlying chip. The pads of the respective chips are connected to a set of interconnections, which are disposed on the substrate. This configuration of stacked chips enables the overall height of the memory module to be reduced because the insulating film prevents the bonding wires from contacting the substrate of the top chips.

摘要翻译： 本文提供具有接合线的多芯片模块（MCM）及其制造方法。 多芯片模块包括基板和顺序层叠的多个芯片。 堆叠在最低芯片上方的至少一个顶部芯片具有覆盖其背面的绝缘膜。 此外，每个堆叠的芯片具有形成在其上表面的周边或边缘上的接合焊盘。 在堆叠的芯片之间插入至少一个绝缘体。 绝缘体暴露底层芯片上的焊盘。 各个芯片的焊盘连接到一组布置在基板上的互连。 堆叠式芯片的这种配置使得由于绝缘膜防止接合线接触顶部芯片的基板而使存储器模块的整体高度减小。