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    Method of programming nonvolatile memory device
    1.
    发明授权
    Method of programming nonvolatile memory device 有权
    非易失性存储器件编程方法

    公开(公告)号：US07760551B2

    公开(公告)日：2010-07-20

    申请号：US12232082

    申请日：2008-09-10

    申请人： Sang-jin Park ,  Kwang-soo Seol ,  Ki-hwan Choi ,  Jung-hun Sung ,  Sang-moo Choi

    发明人： Sang-jin Park ,  Kwang-soo Seol ,  Ki-hwan Choi ,  Jung-hun Sung ,  Sang-moo Choi

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3413 ,  G11C16/3454 ,  G11C16/3486

    摘要： A method of programming a nonvolatile memory device may include applying a program voltage to a memory cell. A supplementary pulse may be applied to the memory cell to facilitate thermalization of charges after the application of the program voltage. A recovery voltage may be applied to the memory cell after the application of the supplementary pulse. A program state of the memory cell may be verified using a verification voltage after the application of the recovery voltage.

    摘要翻译： 非易失性存储器件的编程方法可以包括将程序电压施加到存储单元。 补充脉冲可以施加到存储器单元，以便在施加编程电压之后促进电荷的热化。 在施加补充脉冲之后，可以将复原电压施加到存储单元。 可以在施加恢复电压之后使用验证电压来验证存储器单元的编程状态。

    Method of programming nonvolatile memory device
    2.
    发明申请
    Method of programming nonvolatile memory device 有权
    非易失性存储器件编程方法

    公开(公告)号：US20090067247A1

    公开(公告)日：2009-03-12

    申请号：US12232082

    申请日：2008-09-10

    申请人： Sang-jin Park ,  Kwang-soo Seol ,  Ki-hwan Choi ,  Jung-hun Sung ,  Sang-moo Choi

    发明人： Sang-jin Park ,  Kwang-soo Seol ,  Ki-hwan Choi ,  Jung-hun Sung ,  Sang-moo Choi

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3413 ,  G11C16/3454 ,  G11C16/3486

    摘要： A method of programming a nonvolatile memory device may include applying a program voltage to a memory cell. A supplementary pulse may be applied to the memory cell to facilitate thermalization of charges after the application of the program voltage. A recovery voltage may be applied to the memory cell after the application of the supplementary pulse. A program state of the memory cell may be verified using a verification voltage after the application of the recovery voltage.

    摘要翻译： 非易失性存储器件的编程方法可以包括将程序电压施加到存储单元。 补充脉冲可以施加到存储器单元，以便在施加编程电压之后促进电荷的热化。 在施加补充脉冲之后，可以将复原电压施加到存储单元。 可以在施加恢复电压之后使用验证电压来验证存储器单元的编程状态。

    Methods for testing a group of semiconductor devices simultaneously, and devices amenable to such methods of testing
    5.
    发明授权
    Methods for testing a group of semiconductor devices simultaneously, and devices amenable to such methods of testing 失效
    同时测试一组半导体器件的方法，以及适合于这种测试方法的设备

    公开(公告)号：US06483759B1

    公开(公告)日：2002-11-19

    申请号：US09607788

    申请日：2000-06-30

    申请人： Ki-hwan Choi ,  Young-ho Lim

    发明人： Ki-hwan Choi ,  Young-ho Lim

    IPC分类号： G11C2900

    CPC分类号： G11C29/48 ,  G11C29/006 ,  G11C29/02 ,  G11C29/50

    摘要： Semiconductor devices are specially made to be amenable to group testing, with special testing apparatus. The devices include at least one additional pad, and a special circuit that includes at least one fuse. After DC testing, the fuse may be cut if the device is flawed. The power supply is then redirected through the additional pad for subsequent AC testing. The circuit is such that, if the fuse were cut, the device is removed from the group, so as not to affect the other devices of the group. But if the fuse were not cut, the device is included for the AC testing.

    摘要翻译： 半导体器件专门用于通过专用测试仪器进行组合测试。 这些装置包括至少一个附加的焊盘和包括至少一个熔丝的特殊电路。 直流测试后，如果设备有缺陷，保险丝可能被切断。 然后将电源重新定向到附加焊盘，以便后续的AC测试。 电路如此，如果保险丝被切断，则将该装置从组中移除，以免影响组中的其他装置。 但是如果保险丝没有被切断，则该设备被包括在交流测试中。

    Method for erasing data stored in a nonvolatile memory device
    6.
    发明授权
    Method for erasing data stored in a nonvolatile memory device 失效
    擦除存储在非易失性存储器件中的数据的方法

    公开(公告)号：US5940326A

    公开(公告)日：1999-08-17

    申请号：US62238

    申请日：1998-04-17

    申请人： Ki-hwan Choi

    发明人： Ki-hwan Choi

    IPC分类号： G11C16/02 ,  G11C16/06 ,  G11C16/16 ,  G11C7/00

    CPC分类号： G11C16/16

    摘要： A method for erasing data stored in a memory having a plurality of memory sectors is disclosed, including the steps of loading at least a dummy address bit and a plurality of address bits, checking whether an address corresponding to a first sector has been latched, and recycling the checking operation against a second sector when the address of the first sector is not latched, and performing an erase operation for a sector assigned to an address latched therein until the erase operation is done for a last sector. The address includes the dummy address bit and the address bits, so that a coding logic can be simplified without identifying with the logic configuration of a programming mode.

    摘要翻译： 公开了一种用于擦除存储在具有多个存储器扇区的存储器中的数据的方法，包括以下步骤：至少加载虚拟地址位和多个地址位，检查对应于第一扇区的地址是否已被锁存;以及 当第一扇区的地址未被锁存时，对第二扇区进行检查操作，并且对分配给其中锁存的地址的扇区执行擦除操作，直到对最后扇区进行擦除操作为止。 该地址包括虚拟地址位和地址位，使得可以简化编码逻辑而不用编程模式的逻辑配置进行识别。

    Flash memory device and read method
    7.
    发明授权
    Flash memory device and read method 有权
    闪存设备和读取方式

    公开(公告)号：US08139417B2

    公开(公告)日：2012-03-20

    申请号：US12615526

    申请日：2009-11-10

    申请人： Hyung-gon Kim ,  Ki-hwan Choi

    发明人： Hyung-gon Kim ,  Ki-hwan Choi

    IPC分类号： G11C11/34

    CPC分类号： G11C8/10 ,  G11C11/5621 ,  G11C16/04 ,  G11C16/10

    摘要： A flash memory device includes a word line decoder configured to receive a row address, and decode a selected word line and a neighboring non-selected word line corresponding to the row address during a read operation, and a word line driver configured to receive data identifying the selected word line and the neighboring non-selected word line from the word line decoder, and applying a read voltage to the selected word line, a first voltage to non-selected word lines other than the neighboring non-selected word line, and a second voltage to the neighboring non-selected word line.

    摘要翻译： 闪速存储器件包括：字线解码器，被配置为在读取操作期间接收行地址，并对与行地址相对应的选定字线和相邻的未选择字线进行解码，以及字线驱动器，被配置为接收标识的数据 所选择的字线和来自字线解码器的相邻的未选择的字线，以及向所选择的字线施加读取电压，将第一电压施加到除了相邻未选择字线之外的非选择字线，以及 第二电压到相邻的未选择的字线。

    Methods for testing a group of semiconductor devices simultaneously, and devices amenable to such methods of testing
    8.
    发明授权
    Methods for testing a group of semiconductor devices simultaneously, and devices amenable to such methods of testing 失效
    同时测试一组半导体器件的方法，以及适合于这种测试方法的设备

    公开(公告)号：US06492832B2

    公开(公告)日：2002-12-10

    申请号：US10170911

    申请日：2002-06-12

    申请人： Ki-hwan Choi ,  Young-ho Lim

    发明人： Ki-hwan Choi ,  Young-ho Lim

    IPC分类号： G01R3126

    CPC分类号： G11C29/48 ,  G11C29/006 ,  G11C29/02 ,  G11C29/50

    摘要： Methods are provided for testing many semiconductor devices simultaneously. The devices are connected in a group, and checked for DC-type defects. Those identified to have such a defect are electrically disconnected from the group, and thus also from further group testing. Then testing in the AC mode is performed. The disconnected devices do not sense the AC testing, and the defect does not affect the testing of the others. Semiconductor devices are also provided that are amenable to such testing. These include additional pads, and a special circuit that includes at least one fuse. Disconnection is by cutting the fuse of a device identified to be defective. While afterwards testing for AC-type defects, the power supply and the ground is applied through the additional pads. This grounds the power line of defective chips.

    摘要翻译： 提供了同时测试许多半导体器件的方法。 设备连接在一起，检查DC型缺陷。 识别为具有这种缺陷的那些电极与组电断开，因此也进一步进行组测试。 然后进行AC模式的测试。 断开的设备不会感测到AC测试，并且缺陷不会影响其他测试。 还提供了适合于这种测试的半导体器件。 这些包括额外的焊盘和包括至少一个保险丝的特殊电路。 断开是通过切断被识别为有缺陷的设备的保险丝。 然后在测试交流型缺陷时，通过附加焊盘施加电源和接地。 这使得有缺陷的芯片的电源线接地。