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    Planar and nanowire field effect transistors
    3.
    发明授权
    Planar and nanowire field effect transistors 失效
    平面和纳米线场效应晶体管

    公开(公告)号：US08455334B2

    公开(公告)日：2013-06-04

    申请号：US12631342

    申请日：2009-12-04

    申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    IPC分类号： H01L21/84

    CPC分类号： H01L29/78696 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66772

    摘要： A method for forming an integrated circuit, the method includes forming a first nanowire suspended above an insulator substrate, the first nanowire attached to a first silicon on insulator (SOI) pad region and a second SOI pad region that are disposed on the insulator substrate, a second nanowire disposed on the insulator substrate attached to a third SOI pad region and a fourth SOI pad region that are disposed on the insulator substrate, and a SOI slab region that is disposed on the insulator substrate, and forming a first gate surrounding a portion of the first nanowire, a second gate on a portion of the second nanowire, and a third gate on a portion of the SOI slab region.

    摘要翻译： 一种用于形成集成电路的方法，所述方法包括形成悬置在绝缘体衬底上的第一纳米线，所述第一纳米线附接到绝缘体上的第一绝缘体（SOI）焊盘区域和设置在所述绝缘体衬底上的第二SOI焊盘区域， 布置在绝缘体基板上的第二纳米线，其连接到设置在绝缘体基板上的第三SOI焊盘区域和第四SOI焊盘区域，以及SOI板状区域，其设置在绝缘体基板上，并且形成围绕部分的第一栅极 的第一纳米线，第二纳米线的一部分上的第二栅极和SOI板区域的一部分上的第三栅极。

    DIFFERENT THICKNESS OXIDE SILICON NANOWIRE FIELD EFFECT TRANSISTORS
    4.
    发明申请
    DIFFERENT THICKNESS OXIDE SILICON NANOWIRE FIELD EFFECT TRANSISTORS 失效
    不同厚度的氧化硅纳米线场效应晶体管

    公开(公告)号：US20110133280A1

    公开(公告)日：2011-06-09

    申请号：US12631148

    申请日：2009-12-04

    申请人： Sarunya Bangsaruntip ,  Andres Bryant ,  Guy M. Cohen ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Andres Bryant ,  Guy M. Cohen ,  Jeffrey W. Sleight

    IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/78696 ,  H01L29/42392

    摘要： A method (that produces a structure) patterns at least two wires of semiconductor material such that a first wire of the wires has a larger perimeter than a second wire of the wires. The method performs an oxidation process simultaneously on the wires to form a first gate oxide on the first wire and a second gate oxide on the second wire. The first gate oxide is thicker than the second gate oxide. The method also forms gate conductors over the first gate oxide and the second gate oxide, forms sidewall spacers on the gate conductors, and dopes portions of the first wire and the second wire not covered by the sidewall spacers and the gate conductors to form source and drain regions within the first wire and the second wire.

    摘要翻译： 产生结构的方法（图案）至少形成两条半导体材料线，使得电线的第一线具有比电线的第二线更大的周长。 该方法在导线上同时进行氧化处理，以在第一布线上形成第一栅极氧化物，在第二布线上形成第二栅极氧化物。 第一栅极氧化物比第二栅极氧化物厚。 该方法还在第一栅极氧化物和第二栅极氧化物上形成栅极导体，在栅极导体上形成侧壁间隔物，以及第一导线和第二导线的掺杂部分未被侧壁间隔物和栅极导体覆盖以形成源极和 第一线和第二线内的漏极区。

    SELF-ALIGNED CONTACTS FOR NANOWIRE FIELD EFFECT TRANSISTORS
    5.
    发明申请
    SELF-ALIGNED CONTACTS FOR NANOWIRE FIELD EFFECT TRANSISTORS 有权
    用于纳米效应晶体管的自对准接触

    公开(公告)号：US20110133165A1

    公开(公告)日：2011-06-09

    申请号：US12631213

    申请日：2009-12-04

    申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    IPC分类号： H01L29/66 ,  H01L21/336

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823418 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/78696

    摘要： A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a capping layer on the gate structure; forming a first spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, forming a hardmask layer on the capping layer and the first spacer, removing exposed portions of the nanowire, epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region, forming a silicide material in the epitaxially grown doped semiconductor material, and forming a conductive material on the source and drain regions.

    摘要翻译： 形成纳米线场效应晶体管（FET）器件的方法包括在半导体衬底上形成纳米线，在纳米线的一部分周围形成栅极结构，在栅极结构上形成覆盖层; 形成邻近所述栅极的侧壁和从所述栅极延伸的纳米线的周围的第一间隔物，在所述覆盖层和所述第一间隔物上形成硬掩模层，去除所述纳米线的暴露部分，在暴露的横截面上外延生长掺杂半导体材料 以形成源极区和漏极区，在外延生长的掺杂半导体材料中形成硅化物材料，并在源极和漏极区上形成导电材料。

    Generation of multiple diameter nanowire field effect transistors
    8.
    发明授权
    Generation of multiple diameter nanowire field effect transistors 有权
    生成多直径纳米线场效应晶体管

    公开(公告)号：US08519479B2

    公开(公告)日：2013-08-27

    申请号：US12778526

    申请日：2010-05-12

    申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Jeffrey W. Sleight

    IPC分类号： H01L27/12

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/302 ,  H01L21/3247 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

    摘要： A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming first and second nanowire channels connected at each end to semiconductor pads at first and second wafer regions, respectively, with second nanowire channel sidewalls being misaligned relative to a crystallographic plane of the semiconductor more than first nanowire channel sidewalls and displacing the semiconductor toward an alignment condition between the sidewalls and the crystallographic plane such that thickness differences between the first and second nanowire channels reflect the greater misalignment of the second nanowire channel sidewalls.

    摘要翻译： 提供了修改具有设置在绝缘体上的半导体的晶片的方法，并且包括分别在第一和第二晶片区域处形成分别连接到半导体焊盘的第一和第二纳米线通道，其中第二纳米线通道侧壁相对于晶体学不对准 半导体的平面超过第一纳米线通道侧壁并将半导体移向侧壁和结晶平面之间的对准状态，使得第一和第二纳米线通道之间的厚度差异反映了第二纳米线通道侧壁的较大的未对准。

    Nanowire Field Effect Transistor Device
    9.
    发明申请
    Nanowire Field Effect Transistor Device 有权
    纳米线场效应晶体管器件

    公开(公告)号：US20130112937A1

    公开(公告)日：2013-05-09

    申请号：US13292336

    申请日：2011-11-09

    申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Jeffrey W. Sleight

    IPC分类号： H01L29/772 ,  H01L21/336 ,  H01L29/775 ,  B82Y40/00 ,  B82Y99/00

    CPC分类号： B82Y10/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696 ,  Y10S977/938

    摘要： A method for forming a field effect transistor device includes forming a nanowire suspended above a substrate, forming a dummy gate stack on a portion of the substrate and around a portion of the nanowire, removing exposed portions of the nanowire, epitaxially growing nanowire extension portions from exposed portions of the nanowire, depositing a layer of semiconductor material over exposed portions of the substrate, the dummy gate stack and the nanowire extension portions, and removing portions of the semiconductor material to form sidewall contact regions arranged adjacent to the dummy gate stack and contacting the nanowire extension portions.

    摘要翻译： 一种用于形成场效应晶体管器件的方法包括形成悬浮在衬底上的纳米线，在衬底的一部分和纳米线的一部分周围形成虚拟栅极堆叠，从纳米线的外延生长纳米线延伸部分的外延生长 暴露的纳米线部分，在衬底的暴露部分，伪栅极堆叠和纳米线延伸部分上沉积半导体材料层，以及去除半导体材料的部分以形成邻近虚拟栅极堆叠布置的侧壁接触区域， 纳米线延伸部分。