公开(公告)号：US08350389B2

公开(公告)日：2013-01-08

申请号：US12923789

申请日：2010-10-07

申请人： Satoshi Itaya ,  Kayoko Shibata ,  Shoji Azuma ,  Akira Ide

发明人： Satoshi Itaya ,  Kayoko Shibata ,  Shoji Azuma ,  Akira Ide

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/76898 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014

摘要： A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.

摘要翻译： 半导体器件包括多个核心芯片和控制芯片芯片的接口芯片。 芯片芯片和接口芯片中的每一个都包括穿透半导体衬底的多个穿过硅通孔和分别连接到通孔硅通孔的多个焊盘。 贯通硅通孔包括供电电源电位或接地电位的电源系统的贯穿硅通孔，以及供给各种信号的信号系统的通孔硅通孔。 在焊盘中，连接到电源系统的贯穿硅通孔的焊盘的至少一个尺寸大于连接到信号系统的通过硅通孔的焊盘的尺寸。 因此，可以确保更大的寄生电容。

公开(公告)号：US20110084385A1

公开(公告)日：2011-04-14

申请号：US12923789

申请日：2010-10-07

申请人： Satoshi Itaya ,  Kayoko Shibata ,  Shoji Azuma ,  Akira Ide

发明人： Satoshi Itaya ,  Kayoko Shibata ,  Shoji Azuma ,  Akira Ide

IPC分类号： H01L23/485

CPC分类号： H01L21/76898 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014

摘要： A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.

摘要翻译： 半导体器件包括多个核心芯片和控制芯片芯片的接口芯片。 芯片芯片和接口芯片中的每一个都包括穿透半导体衬底的多个穿过硅通孔和分别连接到通孔硅通孔的多个焊盘。 贯通硅通孔包括供电电源电位或接地电位的电源系统的贯穿硅通孔，以及供给各种信号的信号系统的通孔硅通孔。 在焊盘中，连接到电源系统的贯穿硅通孔的焊盘的至少一个尺寸大于连接到信号系统的通过硅通孔的焊盘的尺寸。 因此，可以确保更大的寄生电容。

公开(公告)号：US08498831B2

公开(公告)日：2013-07-30

申请号：US12923831

申请日：2010-10-08

申请人： Akira Ide ,  Hideyuki Yoko ,  Kayoko Shibata ,  Kenichi Tanamachi ,  Takanori Eguchi ,  Yasuyuki Shigezane ,  Naoki Ogawa ,  Kazuo Hidaka

发明人： Akira Ide ,  Hideyuki Yoko ,  Kayoko Shibata ,  Kenichi Tanamachi ,  Takanori Eguchi ,  Yasuyuki Shigezane ,  Naoki Ogawa ,  Kazuo Hidaka

IPC分类号： G06F19/00

CPC分类号： G11C29/02 ,  G11C5/04 ,  G11C29/025 ,  H01L2224/16 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal.

摘要翻译： 包括将接口芯片电连接到核心芯片的一个或多个内部信号线。 接口芯片包括将电流输出到内部布线的第一电路，并且芯片芯片包括向第一内部信号线输出电流的第二电路。 接口芯片包括确定电路，其具有连接到由第一电路输出的电流流过的内部布线的第一输入端子和连接到接口芯片中的第一内部信号线的一端的第二输入端子，并且输出 根据第一输入端子的电压与第二输入端子的电压之间的电位差的电压。

公开(公告)号：US20110093224A1

公开(公告)日：2011-04-21

申请号：US12923831

申请日：2010-10-08

申请人： Akira Ide ,  Hideyuki Yoko ,  Kayoko Shibata ,  Kenichi Tanamachi ,  Takanori Eguchi ,  Yasuyuki Shigezane ,  Naoki Ogawa ,  Kazuo Hidaka

发明人： Akira Ide ,  Hideyuki Yoko ,  Kayoko Shibata ,  Kenichi Tanamachi ,  Takanori Eguchi ,  Yasuyuki Shigezane ,  Naoki Ogawa ,  Kazuo Hidaka

IPC分类号： G01R19/00 ,  G06F19/00

CPC分类号： G11C29/02 ,  G11C5/04 ,  G11C29/025 ,  H01L2224/16 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal.

摘要翻译： 包括将接口芯片电连接到核心芯片的一个或多个内部信号线。 接口芯片包括将电流输出到内部布线的第一电路，并且芯片芯片包括向第一内部信号线输出电流的第二电路。 接口芯片包括确定电路，其具有连接到由第一电路输出的电流流过的内部布线的第一输入端子和连接到接口芯片中的第一内部信号线的一端的第二输入端子，并且输出 根据第一输入端子的电压与第二输入端子的电压之间的电位差的电压。

公开(公告)号：US20110104852A1

公开(公告)日：2011-05-05

申请号：US13005350

申请日：2011-01-12

申请人： Masakazu ISHINO ,  Hiroaki Ikeda ,  Kayoko Shibata

发明人： Masakazu ISHINO ,  Hiroaki Ikeda ,  Kayoko Shibata

IPC分类号： H01L21/50

CPC分类号： H01L21/6835 ,  G11C5/02 ,  G11C5/025 ,  H01L23/481 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

摘要翻译： 半导体存储器件具有多个芯片和接口芯片，其规格可以容易地改变，同时抑制其可靠性的劣化。 该器件具有插入器芯片。 连接到芯片的第一内部电极形成在插入器芯片的第一表面上。 连接到接口芯片的第二内部电极和连接到外部电极的第三内部电极形成在插入器芯片的第二表面上。 只要需要，接口芯片可以安装在插入器芯片的第二表面上。 因此，只要客户要求的适当的接口芯片安装在插入器芯片上，存储器件就可以具有对客户所期望的任何规格。 因此，核心芯片不需要以裸芯片的形式大量存放。

公开(公告)号：US07489030B2

公开(公告)日：2009-02-10

申请号：US11635500

申请日：2006-12-08

申请人： Kayoko Shibata ,  Hiroaki Ikeda ,  Yoshihiko Inoue ,  Hitoshi Miwa ,  Tatsuya Ijima

发明人： Kayoko Shibata ,  Hiroaki Ikeda ,  Yoshihiko Inoue ,  Hitoshi Miwa ,  Tatsuya Ijima

IPC分类号： H01L23/02

CPC分类号： H01L25/18 ,  G11C5/04 ,  G11C29/02 ,  G11C29/022 ,  G11C29/70 ,  H01L21/485 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599

摘要： As a defective contact recovery elements, a stacked semiconductor device include a parallel arrangement system in which signal paths are multiplexed, and a defective contact recovery circuit operable to switch a signal path into an auxiliary signal path. The parallel arrangement system is used in a case where the number of signals is small and a very high speed operation is required because of a serial data transfer. The defective contact recovery circuit is used in a case where the number of signals is large because of a parallel data transfer.

摘要翻译： 作为有缺陷的接触恢复元件，堆叠半导体器件包括其中信号路径被复用的并行布置系统，以及可操作以将信号路径切换到辅助信号路径的缺陷接触恢复电路。 在串行数据传输的情况下，使用并行布置系统，并且需要非常高速的操作。 在由于并行数据传送而导致信号数量大的情况下使用有缺陷接触恢复电路。

公开(公告)号：US20070117317A1

公开(公告)日：2007-05-24

申请号：US11560898

申请日：2006-11-17

申请人： Hiroaki Ikeda ,  Kayoko Shibata ,  Junji Yamada

发明人： Hiroaki Ikeda ,  Kayoko Shibata ,  Junji Yamada

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： G11C5/025

摘要： In a three-dimensional stacked memory having through electrodes, no optimal layer arrangement, bank arrangement, control methods have been established, and thus optimal methods are desired to be established. A stacked memory includes memory core layers, an interposer, and an IF chip. By stacking memory core layers having the same arrangement, it is possible to cope with both of no-oparity operation and parity operation. Further, bank designation irrespective of the number of stacks of the memory core layers can be achieved by assignment of a row address and a bank address. Further, the IF chip has refresh counters for performing a refresh control of the stacked memory. This arrangement provides a stacked memory including stacked memory core layers having through electrodes.

摘要翻译： 在具有通过电极的三维堆叠存储器中，没有建立最优层布置，库布置，控制方法，因此希望建立最佳方法。 堆叠存储器包括存储器核心层，插入器和IF芯片。 通过堆叠具有相同布置的存储器核心层，可以处理无视操作和奇偶校验操作两者。 此外，可以通过分配行地址和银行地址来实现与存储器核心层的堆栈数无关的库指定。 此外，IF芯片具有用于执行堆叠存储器的刷新控制的刷新计数器。 这种布置提供了包括具有通过电极的堆叠的存储器芯层的堆叠存储器。

公开(公告)号：US06661092B2

公开(公告)日：2003-12-09

申请号：US10205040

申请日：2002-07-25

申请人： Kayoko Shibata ,  Yoji Nishio

发明人： Kayoko Shibata ,  Yoji Nishio

IPC分类号： H01L2334

CPC分类号： G11C5/147 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory module is provided with a resistor serving as an impedance adjuster which is connected directly or indirectly to an output terminal of an output transistor of a C/A register. The resistor adjusts the output impedance of the C/A register viewed from an input terminal of a C/A bus in such a manner that the output impedance becomes substantially constant within an operating voltage range of an internal signal output from the C/A register. The memory module is further provided with a capacitor serving as a rise time/fall time adjuster which adjusts rise time and fall time of the internal signal to specific values such that satisfactory waveforms are obtained.

摘要翻译： 存储器模块设置有用作阻抗调节器的电阻器，其直接或间接地连接到C / A寄存器的输出晶体管的输出端子。 该电阻调节从C / A总线的输入端子观察的C / A寄存器的输出阻抗，使得输出阻抗在从C / A寄存器输出的内部信号的工作电压范围内变得基本恒定 。 存储器模块还具有用作上升时间/下降时间调节器的电容器，其将内部信号的上升时间和下降时间调整到特定值，从而获得令人满意的波形。

公开(公告)号：US08907463B2

公开(公告)日：2014-12-09

申请号：US13094214

申请日：2011-04-26

申请人： Kayoko Shibata ,  Hiroaki Ikeda

发明人： Kayoko Shibata ,  Hiroaki Ikeda

IPC分类号： H01L23/02 ,  H01L25/065 ,  H01L23/535 ,  H01L23/544

CPC分类号： G11C11/407 ,  H01L23/5226 ,  H01L23/535 ,  H01L23/544 ,  H01L25/0657 ,  H01L2223/5444 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05599

摘要： A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.

摘要翻译： 公开了一种包括多个半导体芯片和多个通线组的半导体器件。 每个通线组由唯一数量的通线组成。 与通过线组相关联的数字彼此互为互补。 当对于每条直线组选择其中一根直线时，半导体芯片中的一个通过多条通线组中所选择的直通线的组合来指定。

公开(公告)号：US08847221B2

公开(公告)日：2014-09-30

申请号：US11870550

申请日：2007-10-11

申请人： Kayoko Shibata

发明人： Kayoko Shibata

IPC分类号： H01L23/58 ,  G01R31/3185 ,  G11C29/02 ,  H01L21/66 ,  H01L23/48 ,  G11C29/50

CPC分类号： G01R31/318513 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C2029/5006 ,  H01L22/32 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2924/13091 ,  H01L2924/3011 ,  H01L2924/00

摘要： A stacked semiconductor device includes: an internal circuit; a through electrode provided to penetrate through a semiconductor substrate; a test wiring to which a predetermined potential different from a substrate potential is supplied at a time of a test; a first switch arranged between the through electrode and the internal circuit; a second switch arranged between the through electrode and the test wiring; and a control circuit that exclusively turns on the first and the second switches. Thereby, it becomes possible to perform an insulation test in a state that the through electrode and the internal circuit are cut off. Thus, even when a slight short-circuit that does not lead to a current defect occurs, the short circuit can be detected.

摘要翻译： 叠层半导体器件包括：内部电路; 设置成贯通半导体基板的贯通电极; 在测试时提供与基板电位不同的预定电位的测试布线; 布置在所述通孔电极和所述内部电路之间的第一开关; 布置在所述通孔电极和所述测试布线之间的第二开关; 以及专门打开第一和第二开关的控制电路。 由此，可以在切断贯通电极和内部电路的状态下进行绝缘试验。 因此，即使发生不会导致电流缺陷的轻微短路，也可以检测短路。