公开(公告)号：US07768009B2

公开(公告)日：2010-08-03

申请号：US12196798

申请日：2008-08-22

申请人： Satoshi Kobayashi ,  Ikuko Kawamata ,  Koji Dairiki ,  Shigeki Komori ,  Toshiyuki Isa ,  Shunpei Yamazaki

发明人： Satoshi Kobayashi ,  Ikuko Kawamata ,  Koji Dairiki ,  Shigeki Komori ,  Toshiyuki Isa ,  Shunpei Yamazaki

IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L27/12

CPC分类号： H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.

摘要翻译： 一种包括具有高电特性和高可靠性的薄膜晶体管的显示装置，以及具有高批量生产率的显示装置的制造方法。 在包括反交错通道停止型薄膜晶体管的显示装置中，反交错通道停止型薄膜晶体管包括包含沟道形成区的微晶半导体膜，以及含有杂质元素的杂质区 在微晶半导体膜的沟道形成区域中，在不与源极和漏极重叠的区域中选择性地提供一种导电型。

公开(公告)号：US08133771B2

公开(公告)日：2012-03-13

申请号：US12838115

申请日：2010-07-16

申请人： Satoshi Kobayashi ,  Ikuko Kawamata ,  Koji Dairiki ,  Shigeki Komori ,  Toshiyuki Isa ,  Shunpei Yamazaki

发明人： Satoshi Kobayashi ,  Ikuko Kawamata ,  Koji Dairiki ,  Shigeki Komori ,  Toshiyuki Isa ,  Shunpei Yamazaki

IPC分类号： H01L21/00

CPC分类号： H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.

摘要翻译： 一种包括具有高电特性和高可靠性的薄膜晶体管的显示装置，以及具有高批量生产率的显示装置的制造方法。 在包括反交错通道停止型薄膜晶体管的显示装置中，反交错通道停止型薄膜晶体管包括包含沟道形成区的微晶半导体膜，以及含有杂质元素的杂质区 在微晶半导体膜的沟道形成区域中，在不与源极和漏极重叠的区域中选择性地提供一种导电型。

公开(公告)号：US08389993B2

公开(公告)日：2013-03-05

申请号：US13361998

申请日：2012-01-31

申请人： Satoshi Kobayashi ,  Ikuko Kawamata ,  Koji Dairiki ,  Shigeki Komori ,  Toshiyuki Isa ,  Shunpei Yamazaki

发明人： Satoshi Kobayashi ,  Ikuko Kawamata ,  Koji Dairiki ,  Shigeki Komori ,  Toshiyuki Isa ,  Shunpei Yamazaki

IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L27/12

CPC分类号： H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.

摘要翻译： 一种包括具有高电特性和高可靠性的薄膜晶体管的显示装置，以及具有高批量生产率的显示装置的制造方法。 在包括反交错通道停止型薄膜晶体管的显示装置中，反交错通道停止型薄膜晶体管包括包含沟道形成区的微晶半导体膜，以及含有杂质元素的杂质区 在微晶半导体膜的沟道形成区域中，在不与源极和漏极重叠的区域中选择性地提供一种导电型。

公开(公告)号：US07786485B2

公开(公告)日：2010-08-31

申请号：US12390144

申请日：2009-02-20

申请人： Koji Dairiki ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae ,  Satoshi Kobayashi

发明人： Koji Dairiki ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae ,  Satoshi Kobayashi

IPC分类号： H01L27/14 ,  H01L29/04 ,  H01L29/15

CPC分类号： H01L27/1214 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765

摘要： A thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions so as to be overlapped at least partly with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of conductive layers which is overlapped over the gate insulating layers at least partly with the gate electrode and the impurity semiconductor layers, and is disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer which is in contact with the gate insulating layer and the pair of conductive layers and is extended between the pair of conductive layers.

摘要翻译： 薄膜晶体管包括一对杂质半导体层，其中添加赋予一种导电类型的杂质元素以形成源极区和漏极区，以至少部分地与栅电极重叠，栅极绝缘层介于 栅电极和杂质半导体层; 一对导电层，其至少部分地与所述栅电极和所述杂质半导体层重叠在所述栅极绝缘层上方，并且在沟道长度方向上设置有间隔; 以及与所述栅极绝缘层和所述一对导电层接触并在所述一对导电层之间延伸的非晶半导体层。

公开(公告)号：US07812348B2

公开(公告)日：2010-10-12

申请号：US12390954

申请日：2009-02-23

申请人： Koji Dairiki ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae ,  Satoshi Kobayashi

发明人： Koji Dairiki ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae ,  Satoshi Kobayashi

IPC分类号： H01L27/14

CPC分类号： H01L29/78609 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/78669

摘要： A thin-film transistor in which problems with ON-state current and OFF-state current are solved, and a thin-film transistor capable of high-speed operation. The thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions, provided with a space therebetween so as to be overlapped with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of semiconductor layers in which an impurity element which serves as an acceptor is added, overlapped over the gate insulating layers with the gate electrode and the impurity semiconductor layers, and disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer being in contact with the gate insulating layer and the pair of semiconductor layers and extended between the pair of semiconductor layers.

摘要翻译： 解决了导通状态电流和截止电流的问题的薄膜晶体管，以及能够进行高速运转的薄膜晶体管。 薄膜晶体管包括一对杂质半导体层，其中添加赋予一种导电类型的杂质元素以形成源极和漏极区域，其间具有间隔，以便与具有栅极绝缘层的栅电极重叠 插入在栅电极和杂质半导体层之间; 添加作为受体的杂质元素的一对半导体层，与栅极电极和杂质半导体层重叠在栅极绝缘层上，并且在沟道长度方向上间隔设置; 以及与所述栅绝缘层和所述一对半导体层接触并在所述一对半导体层之间延伸的非晶半导体层。

公开(公告)号：US08120030B2

公开(公告)日：2012-02-21

申请号：US12633067

申请日：2009-12-08

申请人： Hiromichi Godo ,  Satoshi Kobayashi ,  Hidekazu Miyairi ,  Toshiyuki Isa ,  Shunpei Yamazaki

发明人： Hiromichi Godo ,  Satoshi Kobayashi ,  Hidekazu Miyairi ,  Toshiyuki Isa ,  Shunpei Yamazaki

IPC分类号： H01L29/04

CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L29/04

摘要： Off current of a bottom gate thin film transistor in which a semiconductor layer is shielded from light by a gate electrode is reduced. A thin film transistor includes a gate electrode layer; a first semiconductor layer; a second semiconductor layer, provided on and in contact with the first semiconductor layer; a gate insulating layer between and in contact with the gate electrode layer and the first semiconductor layer; impurity semiconductor layers in contact with the second semiconductor layer; and source and drain electrode layers partially in contact with the impurity semiconductor layers and the first and second semiconductor layers. The entire surface of the first semiconductor layer on the gate electrode layer side is covered by the gate electrode layer; and a potential barrier at a portion where the first semiconductor layer is in contact with the source or drain electrode layer is 0.5 eV or more.

摘要翻译： 其中半导体层被栅极电极遮挡光的底栅薄膜晶体管的截止电流减小。 薄膜晶体管包括栅电极层; 第一半导体层; 第二半导体层，设置在第一半导体层上并与第一半导体层接触; 在栅极电极层和第一半导体层之间并与之接触的栅极绝缘层; 与第二半导体层接触的杂质半导体层; 以及与杂质半导体层和第一和第二半导体层部分接触的源极和漏极电极层。 栅极电极层侧的第一半导体层的整个表面被栅电极层覆盖; 并且在第一半导体层与源极或漏极电极层接触的部分处的势垒为0.5eV以上。

公开(公告)号：US07791075B2

公开(公告)日：2010-09-07

申请号：US12201130

申请日：2008-08-29

申请人： Satoshi Kobayashi ,  Ikuko Kawamata

发明人： Satoshi Kobayashi ,  Ikuko Kawamata

IPC分类号： H01L29/04

CPC分类号： H01L29/78696 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765

摘要： A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device in high yield are proposed. In a display device including a channel stop thin film transistor with an inverted-staggered structure, the channel stop thin film transistor with the inverted-staggered structure includes a microcrystalline semiconductor film including a channel formation region. An impurity region including an impurity element imparting one conductivity type is formed as selected in a region in the channel formation region of the microcrystalline semiconductor film which does not overlap with a source electrode or a drain electrode. In the channel formation region, a non-doped region, to which the impurity element imparting one conductivity type is not added, is formed between the impurity region, which is a doped region to which the impurity element is added, and the source region or the drain region.

摘要翻译： 提出一种包括具有高电特性和高可靠性的薄膜晶体管的显示装置，以及用于以高产量制造显示装置的方法。 在具有反交错结构的通道阻挡薄膜晶体管的显示装置中，具有反交错结构的通道阻挡薄膜晶体管包括包括沟道形成区域的微晶半导体膜。 在微结晶半导体膜的沟道形成区域中，与源电极或漏电极不重叠的区域中选择包含赋予一种导电类型的杂质元素的杂质区域。 在沟道形成区域中，在作为添加了杂质元素的掺杂区域的杂质区域与源极区域之间形成有不添加赋予一种导电型的杂质元素的非掺杂区域，或 漏极区域。

公开(公告)号：US08420462B2

公开(公告)日：2013-04-16

申请号：US12842067

申请日：2010-07-23

申请人： Satoshi Kobayashi ,  Ikuko Kawamata

发明人： Satoshi Kobayashi ,  Ikuko Kawamata

IPC分类号： H01L21/00

CPC分类号： H01L29/78696 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765

摘要： A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device in high yield are proposed. In a display device including a channel stop thin film transistor with an inverted-staggered structure, the channel stop thin film transistor with the inverted-staggered structure includes a microcrystalline semiconductor film including a channel formation region. An impurity region including an impurity element imparting one conductivity type is formed as selected in a region in the channel formation region of the microcrystalline semiconductor film which does not overlap with a source electrode or a drain electrode. In the channel formation region, a non-doped region, to which the impurity element imparting one conductivity type is not added, is formed between the impurity region, which is a doped region to which the impurity element is added, and the source region or the drain region.

摘要翻译： 提出一种包括具有高电特性和高可靠性的薄膜晶体管的显示装置，以及用于以高产量制造显示装置的方法。 在具有反交错结构的通道阻挡薄膜晶体管的显示装置中，具有反交错结构的通道阻挡薄膜晶体管包括包括沟道形成区域的微晶半导体膜。 在微结晶半导体膜的沟道形成区域中，与源电极或漏电极不重叠的区域中选择包含赋予一种导电类型的杂质元素的杂质区域。 在沟道形成区域中，在作为添加了杂质元素的掺杂区域的杂质区域与源极区域之间形成有不添加赋予一种导电型的杂质元素的非掺杂区域，或 漏极区域。

公开(公告)号：US08618544B2

公开(公告)日：2013-12-31

申请号：US13167762

申请日：2011-06-24

申请人： Koji Dairiki ,  Takayuki Ikeda ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Hiromichi Godo ,  Daisuke Kawae ,  Takayuki Inoue ,  Satoshi Kobayashi

发明人： Koji Dairiki ,  Takayuki Ikeda ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Hiromichi Godo ,  Daisuke Kawae ,  Takayuki Inoue ,  Satoshi Kobayashi

IPC分类号： H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L29/78618 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added.

摘要翻译： 为了改善薄膜晶体管的导通电流和截止电流的问题，薄膜晶体管包括一对杂质半导体层，赋予一种导电类型的杂质元素，在其间具有间隔; 在所述栅极绝缘层上与所述栅电极和添加了赋予一种导电类型的杂质元素的所述一对杂质半导体层中的一个重叠的导电层; 以及非晶半导体层，其被连续地设置在赋予一种导电类型的杂质元素的一对杂质半导体层之间，使得非晶半导体层从导电层延伸到栅极绝缘层上并且接触 同时添加赋予一种导电类型的杂质元素的一对杂质半导体层。

公开(公告)号：US07968880B2

公开(公告)日：2011-06-28

申请号：US12391398

申请日：2009-02-24

申请人： Koji Dairiki ,  Takayuki Ikeda ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Hiromichi Godo ,  Daisuke Kawae ,  Takayuki Inoue ,  Satoshi Kobayashi

发明人： Koji Dairiki ,  Takayuki Ikeda ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Hiromichi Godo ,  Daisuke Kawae ,  Takayuki Inoue ,  Satoshi Kobayashi

IPC分类号： H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L29/78618 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added.

摘要翻译： 为了改善薄膜晶体管的导通电流和截止电流的问题，薄膜晶体管包括一对杂质半导体层，赋予一种导电类型的杂质元素，在其间具有间隔; 在所述栅极绝缘层上与所述栅电极和添加了赋予一种导电类型的杂质元素的所述一对杂质半导体层中的一个重叠的导电层; 以及非晶半导体层，其被连续地设置在赋予一种导电类型的杂质元素的一对杂质半导体层之间，使得非晶半导体层从导电层延伸到栅极绝缘层上并且接触 同时添加赋予一种导电类型的杂质元素的一对杂质半导体层。