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公开(公告)号：US5815038A
公开(公告)日：1998-09-29
申请号：US635710
申请日：1996-04-22
CPC分类号： H03F1/3241 , H03F2200/198
摘要： A small-sized distortion compensation circuit is disclosed. In a semi-conductor element having three terminals, its gate is used as an input terminal. One of the drain and source is used as an output terminal, and the other is grounded. This structure does not need a conventionally used circuit comprising a complicated combination of distributors, couplers and attenuators, enabling the circuit to be smaller.
摘要翻译： 公开了一种小型失真补偿电路。 在具有三个端子的半导体元件中，其栅极用作输入端子。 其中一个漏极和源极用作输出端子，另一个接地。 该结构不需要常规使用的电路，其包括分配器，耦合器和衰减器的复杂组合，使得电路能够更小。
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2.发明授权Power distribution circuit having center portions of isolation resistors connected together 失效配电电路具有连接在一起的隔离电阻的中心部分
公开(公告)号：US4639694A
公开(公告)日：1987-01-27
申请号：US726322
申请日：1985-04-23
申请人： Kiyoharu Seino , Tadashi Takagi , Fumio Takeda
发明人： Kiyoharu Seino , Tadashi Takagi , Fumio Takeda
CPC分类号： H01P5/12
摘要： A power distribution circuit having two Wilkinson type bi-distribution circuits each of which halves and then distributes its input and formed of a microstrip on a dielectric substrate or a semiconductor substrate. The input terminals of the two Wilkinson type bi-distribution circuits are connected, while substantially middle parts of resistances used as isolation resistances of the respective Wilkinson type bi-distribution circuits are connected by a metallic thin wire.
摘要翻译： 具有两个Wilkinson型双分布电路的功率分配电路，每个电路分两部分，然后将其输入分布并由微带形成在电介质基板或半导体基板上。 两个Wilkinson型双分布电路的输入端子被连接，而用作相应威尔金森型双分布电路的隔离电阻的大体上的中间部分通过金属细线连接。
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公开(公告)号：US08085110B2
公开(公告)日：2011-12-27
申请号：US12523899
申请日：2008-01-30
申请人： Kiyoharu Seino , Masahiko Hunada
发明人： Kiyoharu Seino , Masahiko Hunada
摘要： Since the loss of the conventional microwave device is large, when this device is applied to the microwave component, there are problems; for example, a low-noise amplifier, the noise figure is degraded, and when applied to a high-output amplifier, output and efficiency may be decreased. In particular, in the high-output amplifier of over 100 W class, heat generation at a capacitor which forms the microwave device increases, which causes a problem that the reliability of the microwave device may be decreased. A structure is formed to include a capacitor loaded between two high impedance lines the length of which has ¼ wavelength in the desired frequency band and the characteristic impedance is higher than 50Ω.
摘要翻译： 由于传统的微波装置的损耗大，所以当将该装置应用于微波部件时，存在问题; 例如，低噪声放大器，噪声系数降低，并且当应用于高输出放大器时，可以降低输出和效率。 特别地，在100W以上的高输出放大器中，形成微波装置的电容器的发热增加，导致微波器件的可靠性降低的问题。 一种结构被形成为包括负载在两个高阻抗线之间的电容器，其长度在期望频带中具有1/4波长，并且特征阻抗高于50Ω。
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公开(公告)号：US20100019870A1
公开(公告)日：2010-01-28
申请号：US12523899
申请日：2008-01-30
申请人： Kiyoharu Seino , Masahiko Hunada
发明人： Kiyoharu Seino , Masahiko Hunada
IPC分类号： H01P1/00
摘要： Since the loss of the conventional microwave device is large, when this device is applied to the microwave component, there are problems; for example, a low-noise amplifier, the noise figure is degraded, and when applied to a high-output amplifier, output and efficiency may be decreased. In particular, in the high-output amplifier of over 100W class, heat generation at a capacitor which forms the microwave device increases, which causes a problem that the reliability of the microwave device may be decreased. A structure is formed to include a capacitor loaded between two high impedance lines the length of which has ¼ wavelength in the desired frequency band and the characteristic impedance is higher than 50Ω.
摘要翻译： 由于传统的微波装置的损耗大，所以当将该装置应用于微波部件时，存在问题; 例如，低噪声放大器，噪声系数降低，并且当应用于高输出放大器时，可以降低输出和效率。 特别是，在超过100W级的高输出放大器中，形成微波装置的电容器的发热增加，导致微波器件的可靠性降低的问题。 一种结构被形成为包括负载在两个高阻抗线之间的电容器，其长度在期望频带中具有1/4波长并且特征阻抗高于50mega。
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公开(公告)号：US4853649A
公开(公告)日：1989-08-01
申请号：US151625
申请日：1988-02-02
申请人： Kiyoharu Seino , Tadashi Takagi , Fumio Takeda , Yukio Ikeda
发明人： Kiyoharu Seino , Tadashi Takagi , Fumio Takeda , Yukio Ikeda
CPC分类号： H01L27/0605 , H03F3/607
摘要： A distributed FET amplifier comprising an array of FET elements each having a gate terminal, a drain terminal and a source terminal. The gate terminals of the adjacent FET elements are connected by a first inductor, and the drain terminals of the adjacent FET elements are connected by a second inductor. Between the source terminals of each of the FET elements and the ground is connected a parallel circuit comprising a capacitor having a capacitance greater than the gate-source capacitance of the FET element and an impedance element connected in parallel to the capacitor for grounding the direct current. A bias voltage supply circuit for supplying a bias voltage to such as distributed amplifier is also disclosed.
摘要翻译： 一种分布式FET放大器，包括各自具有栅极端子，漏极端子和源极端子的FET元件阵列。 相邻FET元件的栅极端子通过第一电感器连接，并且相邻FET元件的漏极端子通过第二电感器连接。 在每个FET元件的源极端子和地之间连接有并联电路，该并联电路包括具有大于FET元件的栅极 - 源极电容的电容的电容器和与电容器并联连接的用于接地直流电的阻抗元件 。 还公开了一种用于向分布式放大器提供偏置电压的偏置电压供应电路。
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6.发明授权Phase compensation circuit, frequency converter device and active phased array antenna 失效相位补偿电路，变频器和有源相控阵天线公开(公告)号：US06400237B1
公开(公告)日：2002-06-04
申请号：US09443285
申请日：1999-11-19
申请人： Kiyoharu Seino
发明人： Kiyoharu Seino
IPC分类号： H01P118
摘要： A phase compensation circuit includes two first inductive elements connected in series with a main line through which a signal is passed, a series circuit consisting of a capacitor and a variable capacity element which are provided between a connecting point between the first inductive elements and ground, a second inductive element connected in parallel with the series circuit, and a choke circuit connected between the capacitor and the variable capacity element of the series circuit.
摘要翻译： 相位补偿电路包括与信号通过的主线串联连接的两个第一电感元件，由电容器和可变电容元件组成的串联电路，它们设置在第一电感元件和地之间的连接点之间， 与串联电路并联连接的第二感应元件，以及连接在电容器和串联电路的可变电容元件之间的扼流电路。
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公开(公告)号：US5270668A
公开(公告)日：1993-12-14
申请号：US856446
申请日：1992-03-24
申请人： Yukio Ikeda , Gen Toyoshima , Kiyoharu Seino , Tadashi Takagi
发明人： Yukio Ikeda , Gen Toyoshima , Kiyoharu Seino , Tadashi Takagi
CPC分类号： H03F3/601
摘要： A small-sized, high-efficiency semiconductor amplifier exhibits a satisfactory efficiency characteristic over a wide band and a low output level for secondary and tertiary higher harmonics. The semiconductor amplifier is equipped with an output circuit which is composed of a parallel resonance circuit for the secondary higher harmonic of the fundamental-operation frequency, a first connection line, a second connection line, and an open-end line having a length corresponding to approximately 1/4 of the wavelength of the tertiary higher harmonic, the drain terminal of FETs leading to the output circuit being connected to one end of the parallel resonance circuit through the first connection line, an open point being formed at one end of the parallel resonance circuit, the other end of the parallel resonance circuit for the secondary higher harmonic being connected to the open-end line having a length corresponding to approximately 1/4 of the wavelength of the tertiary higher harmonic through the second connection line, the length and width of the first connection line being adjusted to determine the secondary-higher-harmonic load-reflection coefficient of the FETs as seen from the drain thereof to such a value as will maximize the efficiency of the amplifier, the length and width of the second connection line being appropriately adjusted so as to adjust the impedance matching conditions with respect to the fundamental wave.
摘要翻译： 小型，高效率半导体放大器在宽频带上表现出令人满意的效率特性，对于二次和三次高次谐波具有低输出电平。 半导体放大器配备有输出电路，其由用于基波运算频率的次高次谐波的并联谐振电路，第一连接线，第二连接线和开口端线组成，长度对应于 三分之一高次谐波的波长的大约1/4，导通输出电路的FET的漏极端子通过第一连接线连接到并联谐振电路的一端，开口点形成在并联的一端 谐振电路，用于次级高次谐波的并联谐振电路的另一端连接到具有对应于通过第二连接线的三次高次谐波的波长的大约1/4的长度的开路线，长度和 第一连接线的宽度被调整以确定如图f所示的FET的二次高次谐波负载反射系数 将其漏极设定为使放大器的效率最大化的值，适当调整第二连接线的长度和宽度，以便调整相对于基波的阻抗匹配条件。
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公开(公告)号：US4803443A
公开(公告)日：1989-02-07
申请号：US177738
申请日：1988-04-05
申请人： Tadashi Takagi , Kiyoharu Seino , Fumio Takeda
发明人： Tadashi Takagi , Kiyoharu Seino , Fumio Takeda
CPC分类号： H03F3/604
摘要： A microwave power combining FET amplifier includes T-type input and output branch circuits 13, 14 for power splitting and combining, and interstage matching circuits 6a, 6b laterally connected at their mid-points a, b by a resistance circuit 15 which absorbs odd propagation mode waves reflected back from the output combiner due to non-uniformities between the post-stage FETs 4a, 4b.
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