公开(公告)号：US20100164105A1

公开(公告)日：2010-07-01

申请号：US12646173

申请日：2009-12-23

申请人： Satoshi ONAI ,  Minoru Akaishi ,  Hiroshi Ishizeki ,  Yoshiaki Sano

发明人： Satoshi ONAI ,  Minoru Akaishi ,  Hiroshi Ishizeki ,  Yoshiaki Sano

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05556 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01006

摘要： An object is to prevent a failure, such as a wiring separation or a crack, in an insulating film under a copper wire, in a semiconductor device formed by wire-bonding the copper wire on a portion above the copper wiring. A semiconductor device according to the present invention includes a copper wiring formed above a semiconductor substrate, a plated layer formed so as to cover a top surface and side surfaces of the copper wiring, and a copper wire which is wire-bonded on the plated layer above the copper wiring.

摘要翻译： 在通过在铜布线上的部分上引线接合铜线形成的半导体器件中，目的是防止铜线下的绝缘膜中的布线分离或裂纹等的故障。 根据本发明的半导体器件包括形成在半导体衬底上的铜布线，形成为覆盖铜布线的顶表面和侧表面的镀层和在镀层上引线接合的铜线 铜线上方。

公开(公告)号：US08227341B2

公开(公告)日：2012-07-24

申请号：US12646173

申请日：2009-12-23

申请人： Satoshi Onai ,  Minoru Akaishi ,  Hiroshi Ishizeki ,  Yoshiaki Sano

发明人： Satoshi Onai ,  Minoru Akaishi ,  Hiroshi Ishizeki ,  Yoshiaki Sano

IPC分类号： H01L21/44 ,  H01L29/40

CPC分类号： H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05556 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01006

摘要： An object is to prevent a failure, such as a wiring separation or a crack, in an insulating film under a copper wire, in a semiconductor device formed by wire-bonding the copper wire on a portion above the copper wiring. A semiconductor device according to the present invention includes a copper wiring formed above a semiconductor substrate, a plated layer formed so as to cover a top surface and side surfaces of the copper wiring, and a copper wire which is wire-bonded on the plated layer above the copper wiring.

摘要翻译： 在通过在铜布线上的部分上引线接合铜线形成的半导体器件中，目的是防止铜线下的绝缘膜中的布线分离或裂纹等的故障。 根据本发明的半导体器件包括形成在半导体衬底上的铜布线，形成为覆盖铜布线的顶表面和侧表面的镀层和在镀层上引线接合的铜线 铜线上方。

公开(公告)号：US20080230899A1

公开(公告)日：2008-09-25

申请号：US12053168

申请日：2008-03-21

申请人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

发明人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05085 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/3025

摘要： In a semiconductor device according to the present invention, a plurality of opening regions 5 to 8 are formed in an insulating film on a pad electrode 3. A metal layer 9 formed on the pad electrode 3 has a plurality of concave portions 10 to 13 formed therein by covering the opening regions 5 to 8. Moreover, in a peripheral portion at a bottom of each of the concave portions 10 to 13 in the metal layer 9, the metal layer 9 and a Cu plating layer 19 react with each other. By use of this structure, the metal reaction area serves as a current path on the pad electrode 3. Thus, a resistance value on the pad electrode 3 is reduced.

摘要翻译： 在根据本发明的半导体器件中，在焊盘电极3上的绝缘膜中形成多个开口区域5至8。 形成在焊盘电极3上的金属层9通过覆盖开口区域5〜8而形成有多个凹部10〜13。 此外，在金属层9的各凹部10〜13的底部的周边部分中，金属层9和Cu镀层19相互反应。 通过使用该结构，金属反应区域作为焊盘电极3上的电流路径。 因此，焊盘电极3上的电阻值降低。

公开(公告)号：US08013442B2

公开(公告)日：2011-09-06

申请号：US12053168

申请日：2008-03-21

申请人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

发明人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05085 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/3025

摘要： In a semiconductor device according to the present invention, a plurality of opening regions 5 to 8 are formed in an insulating film on a pad electrode 3. A metal layer 9 formed on the pad electrode 3 has a plurality of concave portions 10 to 13 formed therein by covering the opening regions 5 to 8. Moreover, in a peripheral portion at a bottom of each of the concave portions 10 to 13 in the metal layer 9, the metal layer 9 and a Cu plating layer 19 react with each other. By use of this structure, the metal reaction area serves as a current path on the pad electrode 3. Thus, a resistance value on the pad electrode 3 is reduced.

摘要翻译： 在根据本发明的半导体器件中，在焊盘电极3上的绝缘膜中形成多个开口区域5至8.形成在焊盘电极3上的金属层9具有形成的多个凹部10至13 另外，在金属层9的各凹部10〜13的底部的周边部分中，金属层9和Cu镀层19相互反应。 通过使用这种结构，金属反应区域用作焊盘电极3上的电流路径。因此，焊盘电极3上的电阻值减小。

公开(公告)号：US08076781B2

公开(公告)日：2011-12-13

申请号：US12081487

申请日：2008-04-16

申请人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

发明人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

IPC分类号： H01L29/43

CPC分类号： H01L21/76816 ,  H01L21/32051 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53223 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring layer and a second wiring layer and an opening is formed in a spin coated resin film formed on the first metal layer. In the opening, a Cr layer forming a plating metal layer and a Cu plated layer are connected to each other. With this structure, the spaces among crystal grains in portions in the Cr layer on the first metal layer are wide, which causes the portions to be coarse. In the coarse portions in the Cr layer, an alloy layer formed of the second metal layer and the Cu plated layer is formed, and thus, the connection resistance value is reduced.

摘要翻译： 常规的半导体器件具有由于在布线层之间形成氧化膜而导致布线层之间的连接电阻值的降低困难的问题。 在本发明的半导体装置中，第一金属层被嵌入在连接第一布线层和第二布线层的开放区域中，并且在形成在第一金属层上的旋涂树脂膜中形成开口。 在开口中，形成镀覆金属层的Cr层和Cu镀层彼此连接。 利用这种结构，第一金属层上的Cr层中的部分中的晶粒之间的空间很宽，这使得这些部分变粗。 在Cr层的粗糙部分中，形成由第二金属层和Cu镀层形成的合金层，从而降低连接电阻值。

公开(公告)号：US20080258301A1

公开(公告)日：2008-10-23

申请号：US12081487

申请日：2008-04-16

申请人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

发明人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L21/76816 ,  H01L21/32051 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53223 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring layer and a second wiring layer and an opening is formed in a spin coated resin film formed on the first metal layer. In the opening, a Cr layer forming a plating metal layer and a Cu plated layer are connected to each other. With this structure, the spaces among crystal grains in portions in the Cr layer on the first metal layer are wide, which causes the portions to be coarse. In the coarse portions in the Cr layer, an alloy layer formed of the second metal layer and the Cu plated layer is formed, and thus, the connection resistance value is reduced.

摘要翻译： 常规的半导体器件具有由于在布线层之间形成氧化膜而导致布线层之间的连接电阻值的降低困难的问题。 在本发明的半导体装置中，第一金属层被嵌入在连接第一布线层和第二布线层的开放区域中，并且在形成在第一金属层上的旋涂树脂膜中形成开口。 在开口中，形成镀覆金属层的Cr层和Cu镀层彼此连接。 利用这种结构，第一金属层上的Cr层中的部分中的晶粒之间的空间很宽，这使得这些部分变粗。 在Cr层的粗糙部分中，形成由第二金属层和Cu镀层形成的合金层，从而降低连接电阻值。

公开(公告)号：US20070145530A1

公开(公告)日：2007-06-28

申请号：US11635813

申请日：2006-12-08

申请人： Mitsuru Soma ,  Hirotsugu Hata ,  Minoru Akaishi

发明人： Mitsuru Soma ,  Hirotsugu Hata ,  Minoru Akaishi

IPC分类号： H01L27/082

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7322

摘要： In a semiconductor device of the present invention, an epitaxial layer is formed on a P type single crystal silicon substrate. Isolation regions are formed in the epitaxial layer, and are divided into a plurality of element formation regions. An NPN transistor is formed in one of the element formation regions. An N type diffusion layer is formed between a P type isolation region and a P type diffusion layer which is used as a base region of the NPN transistor. This structure makes the base region and the isolation region tend not to be short-circuited. Hence, the breakdown voltage characteristics of the NPN transistor can be improved.

摘要翻译： 在本发明的半导体器件中，在P型单晶硅基板上形成外延层。 隔离区形成在外延层中，并被分成多个元件形成区域。 在一个元件形成区域中形成NPN晶体管。 在P型隔离区域和用作NPN晶体管的基极区域的P型扩散层之间形成N型扩散层。 该结构使得基极区域和隔离区域不会短路。 因此，能够提高NPN晶体管的击穿电压特性。

公开(公告)号：US20070145520A1

公开(公告)日：2007-06-28

申请号：US11635812

申请日：2006-12-08

申请人： Mitsuru Soma ,  Hirotsugu Hata ,  Minoru Akaishi

发明人： Mitsuru Soma ,  Hirotsugu Hata ,  Minoru Akaishi

IPC分类号： H01L29/00

CPC分类号： H01L29/7833 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7322

摘要： In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. One of the epitaxial layers has an impurity concentration higher than that of the other epitaxial layer. The epitaxial layers are divided into a plurality of element formation regions by isolation regions. In one of the element formation regions, an NPN transistor is formed. Moreover, between a P type diffusion layer, which is used as a base region of the NPN transistor, and a P type isolation region, an N type diffusion layer is formed. Use of this structure makes it hard for a short-circuit to occur between the base region and the isolation region. Thus, the breakdown voltage characteristics of the NPN transistor can be improved.

摘要翻译： 在本发明的半导体器件中，在P型单晶硅衬底上形成两个外延层。 一个外延层的杂质浓度高于另一个外延层的杂质浓度。 通过隔离区将外延层分成多个元件形成区域。 在一个元件形成区域中，形成NPN晶体管。 此外，在用作NPN晶体管的基极区域的P型扩散层和P型隔离区域之间，形成N型扩散层。 使用这种结构使得在基极区域和隔离区域之间难以发生短路。 因此，可以提高NPN晶体管的击穿电压特性。

公开(公告)号：US07719081B2

公开(公告)日：2010-05-18

申请号：US11635813

申请日：2006-12-08

申请人： Mitsuru Soma ,  Hirotsugu Hata ,  Minoru Akaishi

发明人： Mitsuru Soma ,  Hirotsugu Hata ,  Minoru Akaishi

IPC分类号： H01L21/8228

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7322

摘要： In a semiconductor device of the present invention, an epitaxial layer is formed on a P type single crystal silicon substrate. Isolation regions are formed in the epitaxial layer, and are divided into a plurality of element formation regions. An NPN transistor is formed in one of the element formation regions. An N type diffusion layer is formed between a P type isolation region and a P type diffusion layer which is used as a base region of the NPN transistor. This structure makes the base region and the isolation region tend not to be short-circuited. Hence, the breakdown voltage characteristics of the NPN transistor can be improved.

摘要翻译： 在本发明的半导体器件中，在P型单晶硅基板上形成外延层。 隔离区形成在外延层中，并被分成多个元件形成区域。 在一个元件形成区域中形成NPN晶体管。 在P型隔离区域和用作NPN晶体管的基极区域的P型扩散层之间形成N型扩散层。 该结构使得基极区域和隔离区域不会短路。 因此，能够提高NPN晶体管的击穿电压特性。

公开(公告)号：US20070009374A1

公开(公告)日：2007-01-11

申请号：US10539507

申请日：2003-11-19

申请人： Minoru Akaishi ,  Keigo Kawamura

发明人： Minoru Akaishi ,  Keigo Kawamura

IPC分类号： C22C1/04

CPC分类号： C04B35/52 ,  B82Y30/00 ,  C04B35/64 ,  C04B35/645 ,  C04B2235/422 ,  C04B2235/427 ,  C04B2235/428 ,  C04B2235/5445 ,  C04B2235/661 ,  C04B2235/781 ,  C04B2235/80 ,  C04B2235/96

摘要： Disclosed is a heat-resistant diamond composite sintered body, which is prepared by sintering an ultrafine-grain synthetic diamond powder having an average grain size of 200 nm or less, without using a sintering aid. The composite sintered body comprises a diamond crystal and a minute amount of non-diamond carbon as a product, and has a Vickers hardness of 85 GPa or more. The composite sintered body is produced by a method comprising enclosing in a Ta or Mo capsule a synthetic diamond powder having an average grain size of 200 nm or less, and heating and pressurizing using an ultrahigh-pressure synthesizing apparatus under thermodynamically stable conditions including a temperature of 2100° C. or more and a pressure of 7.7 GPa or more.

摘要翻译： 公开了一种耐热金刚石复合烧结体，其通过烧结平均粒径为200nm以下的超细晶粒合成金刚石粉末而不使用烧结助剂而制备。 复合烧结体包含金刚石晶体和微量非金刚石碳作为产品，维氏硬度为85GPa以上。 复合烧结体的制造方法包括：在Ta或Mo胶囊中包含平均粒径为200nm以下的合成金刚石粉末，在超高压合成装置的热力学稳定条件下进行加热加压，包括温度 为2100℃以上，压力为7.7GPa以上。