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1.发明授权Plural operand buses of intermediate widths coupling to narrower width integer and wider width floating point superscalar processing core 失效中间宽度的多个操作数总线耦合到较窄宽度的整数和宽宽度的浮点超标量处理核心公开(公告)号：US5903772A
公开(公告)日：1999-05-11
申请号：US920649
申请日：1997-08-15
Applicant: Scott A. White , Michael D. Goddard , William M. Johnson
Inventor： Scott A. White , Michael D. Goddard , William M. Johnson
CPC classification number: G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30094 , G06F9/3814 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
Abstract: A processor core for supporting the concurrent execution of mixed integer and floating point operations includes integer functional units (110) utilizing 32-bit operand data and a floating point functional unit (22) utilizing up to 82-bit operand data. Eight operand busses (30, 31) connect to the functional units to furnish operand data, and five result busses (32) are connected to the functional units to return results. The width of the operand busses is 41 bits, which is sufficient to communicate either integer or floating point data. This is done using an instruction decoder (18) to apportion a floating point operation which operates on 82-bit floating point operand data into multiple suboperations each associated with a 41-bit suboperand. The operand busses and result busses have an expanded data-handling dimension from the standard integer data width of 32 bits to 41 bits for handling the floating point operands. The floating point functional unit recombines the suboperand data into 82-bits for execution of the floating point operation, and partitions the 82-bit result for output to the result busses. In addition, the excess capacity of the result busses during integer transfers is used to communicate integer flags.
Abstract translation: 用于支持并行执行混合整数和浮点运算的处理器核心包括利用32位操作数数据的整数功能单元（110）和利用高达82位操作数数据的浮点功能单元（22）。 八个操作数总线（30,31）连接到功能单元以提供操作数据，并且五个结果总线（32）连接到功能单元以返回结果。 操作数总线的宽度为41位，足以传送整数或浮点数据。 这是使用指令解码器（18）来完成的，以将对82位浮点运算数据进行操作的浮点运算分配成与41位子波段相关的多个子波形。 操作数总线和结果总线具有从32位的标准整数数据宽度到41位的扩展数据处理维度，用于处理浮点操作数。 浮点功能单元将小波段数据重新组合为82位，用于执行浮点运算，并将82位结果分割为结果总线。 此外，整数传输期间结果总线的剩余容量用于通信整数标志。
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2.发明授权Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments 失效具有用于传送操作数段的多个操作数总线的超标量微处理器的混合整数/浮点处理器核
公开(公告)号：US5574928A
公开(公告)日：1996-11-12
申请号：US233563
申请日：1994-04-26
Applicant: Scott A. White , Michael D. Goddard , William M. Johnson
Inventor： Scott A. White , Michael D. Goddard , William M. Johnson
CPC classification number: G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30094 , G06F9/30149 , G06F9/3802 , G06F9/3806 , G06F9/3814 , G06F9/382 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3885
Abstract: A processor core for supporting the concurrent execution of mixed integer and floating point operations includes integer functional units (110) utilizing 32-bit operand data and a floating point functional unit (22) utilizing up to 82-bit operand data. Eight operand busses (30, 31) connect to the functional units to furnish operand data, and five result busses (32) are connected to the functional units to return results. The width of the operand busses is 41 bits, which is sufficient to communicate either integer or floating point data. This is done using an instruction decoder (18) to apportion a floating point operation which operates on 82-bit floating point operand data into multiple suboperations each associated with a 41-bit suboperand. The operand busses and result busses have an expanded data-handling dimension from the standard integer data width of 32 bits to 41 bits for handling the floating point operands. The floating point functional unit recombines the suboperand data into 82-bits for execution of the floating point operation, and partitions the 82-bit result for output to the result busses. In addition, the excess capacity of the result busses during integer transfers is used to communicate integer flags.
Abstract translation: 用于支持并行执行混合整数和浮点运算的处理器核心包括利用32位操作数数据的整数功能单元（110）和利用高达82位操作数数据的浮点功能单元（22）。 八个操作数总线（30,31）连接到功能单元以提供操作数据，并且五个结果总线（32）连接到功能单元以返回结果。 操作数总线的宽度为41位，足以传送整数或浮点数据。 这是使用指令解码器（18）来完成的，以将对82位浮点运算数据进行操作的浮点运算分配成与41位子波段相关的多个子波形。 操作数总线和结果总线具有从32位的标准整数数据宽度到41位的扩展数据处理维度，用于处理浮点操作数。 浮点功能单元将小波段数据重新组合为82位，用于执行浮点运算，并将82位结果分割为结果总线。 此外，整数传输期间结果总线的剩余容量用于通信整数标志。
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3.发明授权Exception handling processor for handling first and second level exceptions with reduced exception latency 失效用于处理第一和第二级别例外的例外处理程序，减少例外时间
公开(公告)号：US5237700A
公开(公告)日：1993-08-17
申请号：US496762
申请日：1990-03-21
Applicant: William M. Johnson , Michael D. Goddard , Tim Olson
Inventor： William M. Johnson , Michael D. Goddard , Tim Olson
CPC classification number: G06F11/1415 , G06F9/3863
Abstract: A processor having improved exception handling capability handles second level exceptions with reduced exception latency. The processor processes instructions in order through a plurality of serial stages. A first set of registers continuously tracks each instruction as it advances from stage to stage. An exception handles processes first level exception conditions and precludes updating of the first set of registers when it processes first level exception conditions to permit the processor to restart at the point of a first level exception condition. A second set of registers continuously tracks the instruction in tandem with the first set of registers, but is updatable during the processing of first level exception conditions by the exception handles. A monitor processes second level exception conditions occurring in the exception handler and precludes the second set of registers from being updated when it processes the second level exception conditions to permit the exception handler to restart from the point of the occurrence of a second level exception condition.
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4.发明授权
公开(公告)号：US08185262B2
公开(公告)日：2012-05-22
申请号：US12763427
申请日：2010-04-20
Applicant: William M. Johnson
Inventor： William M. Johnson
CPC classification number: B64G1/361 , B64G1/281 , G01S3/7862 , G05D1/0883
Abstract: A method of and apparatus for determining and controlling the inertial attitude of a spinning artificial satellite without using a suite of inertial gyroscopes. The method and apparatus operate by tracking three astronomical objects near the Earth's ecliptic pole and the satellite's and/or star tracker's spin axis and processing the track information. The method and apparatus include steps and means for selecting preferably three astronomical objects using a histogram method and determining a square of a first radius (R12) of a track of a first astronomical object; determining a square of a second radius (R22) of a track of a second astronomical object; determining a square of a third radius (R32) of a track of a third astronomical object; determining the inertial attitude of the spin axis using the squares of the first, second, and third radii (R12, R22, and R32) to calculate pitch, yaw, and roll rate; determining a change in the pitch and yaw of the artificial satellite; and controlling on-board generated current flow to various orthogonally-disposed current-carrying loops to act against the Earth's magnetic field and to apply gyroscopic precession to the spinning satellite to correct and maintain its optimum inertial attitude.
Abstract translation: 用于在不使用一套惯性陀螺仪的情况下确定和控制旋转人造卫星的惯性姿态的方法和装置。 该方法和装置通过跟踪地球黄道附近的三个天文物体和卫星和/或星形跟踪器的自旋轴进行操作并处理轨道信息。 所述方法和装置包括使用直方图方法优选地选择三个天文物体并且确定第一天文物体的轨道的第一半径（R12）的平方的步骤和装置; 确定第二天文物体的轨道的第二半径（R22）的平方; 确定第三天文物体的轨道的第三半径（R32）的平方; 使用第一，第二和第三半径（R12，R22和R32）的平方来确定旋转轴的惯性姿态来计算俯仰，偏航和滚动速率; 确定人造卫星的俯仰和偏航的变化; 并且控制板上产生的电流流向各种正交布置的载流回路，以对地球的磁场起作用，并对旋转卫星施加陀螺进动，以校正和保持其最佳惯性姿态。
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公开(公告)号：US08000735B1
公开(公告)日：2011-08-16
申请号：US11001491
申请日：2004-12-01
Applicant: Michael Barclay , Terry Lynn Cole , Richard Powell , William M. Johnson , David W. Smith , Ralf Findeisen , Derek Golightly
Inventor： Michael Barclay , Terry Lynn Cole , Richard Powell , William M. Johnson , David W. Smith , Ralf Findeisen , Derek Golightly
IPC: H04M1/00
CPC classification number: H04W88/02
Abstract: A wireless communications device includes a host processing unit, a modem processing unit, and a memory transport interface. The wireless communications device typically runs a variety of software tasks, some of which require considerably more memory than others. By processing the memory intensive tasks with the host processing unit and assigning tasks requiring high computing power but relatively smaller memory to the modem processor unit, a smaller on-chip memory can be used for the modem processor unit tasks. In addition, by using a messaging transport interface to transfer data between tasks running on different processing units, smaller local memories can be used in place of a shared memory. For example, by allocating and storing L1 tasks at the modem processing unit and allocating/storing L2 and L3 tasks at the host processing unit, duplicate memory components may be reduced or removed, thereby lowering system costs and improving system efficiency.
Abstract translation: 无线通信设备包括主机处理单元，调制解调器处理单元和存储器传输接口。 无线通信设备通常运行各种软件任务，其中一些需要比其他任务更多的存储器。 通过使用主机处理单元处理存储器密集型任务并且为调制解调器处理器单元分配需要高计算能力但是相对较小的存储器的任务，可以使用较小的片上存储器用于调制解调器处理器单元任务。 此外，通过使用消息传送接口在不同处理单元之间运行的任务之间传送数据，可以使用较小的本地存储器代替共享存储器。 例如，通过在调制解调器处理单元分配和存储L1任务并在主处理单元分配/存储L2和L3任务，可以减少或移除重复的存储器组件，从而降低系统成本并提高系统效率。
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6.发明申请
公开(公告)号：US20090222153A1
公开(公告)日：2009-09-03
申请号：US12363959
申请日：2009-02-02
Applicant: William M. Johnson
Inventor： William M. Johnson
CPC classification number: B64G1/281 , B64G1/32 , B64G1/361 , B64G1/363 , B64G1/365 , B64G1/44 , G01S3/7862 , G05D1/0883
Abstract: A method of and apparatus for determining and controlling the inertial attitude of a spinning artificial satellite without using a suite of inertial gyroscopes. The method and apparatus operate by tracking three astronomical objects near the Earth's ecliptic pole and the satellite's and/or star tracker's spin axis and processing the track information. The method and apparatus include steps and means for selecting preferably three astronomical objects using a histogram method and determining a square of a first radius (R12) of a track of a first astronomical object; determining a square of a second radius (R22) of a track of a second astronomical object; determining a square of a third radius (R32) of a track of a third astronomical object; determining the inertial attitude of the spin axis using the squares of the first, second, and third radii (R12, R22, and R32) to calculate pitch, yaw, and roll rate; determining a change in the pitch and yaw of the artificial satellite; and controlling on-board generated current flow to various orthogonally-disposed current-carrying loops to act against the Earth's magnetic field and to apply gyroscopic precession to the spinning satellite to correct and maintain its optimum inertial attitude.
Abstract translation: 用于在不使用一套惯性陀螺仪的情况下确定和控制旋转人造卫星的惯性姿态的方法和装置。 该方法和装置通过跟踪地球黄道附近的三个天文物体和卫星和/或星形跟踪器的自旋轴进行操作并处理轨道信息。 所述方法和装置包括使用直方图方法优选地选择三个天文物体并且确定第一天文物体的轨道的第一半径（R12）的平方的步骤和装置; 确定第二天文物体的轨道的第二半径（R22）的平方; 确定第三天文物体的轨道的第三半径（R32）的平方; 使用第一，第二和第三半径（R12，R22和R32）的平方来确定旋转轴的惯性姿态来计算俯仰，偏航和滚动速率; 确定人造卫星的俯仰和偏航的变化; 并且控制板上产生的电流流向各种正交布置的载流回路，以对地球的磁场起作用，并对旋转卫星施加陀螺进动，以校正和保持其最佳惯性姿态。
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公开(公告)号：US06279101B1
公开(公告)日：2001-08-21
申请号：US08474791
申请日：1995-06-07
Applicant: David B. Witt , William M. Johnson
Inventor： David B. Witt , William M. Johnson
IPC: G06F938
CPC classification number: G06F9/3836 , G06F9/3855 , G06F9/3857
Abstract: A super-scalar microprocessor performs operations upon a plurality of instructions at each of its fetch, decode, execute, and write-back stages. To support such operations, the super-scalar microprocessor includes a dispatch arrangement including an instruction cache for fetching blocks of instructions including a plurality of instructions and an instruction decoder which decodes and dispatches the instructions to functional units for execution. The instruction decoder applies a dispatch criteria to selected instructions of each block of instructions and dispatches the selected instructions which satisfy the dispatch criteria. The dispatch criteria includes the requirement that the instructions be dispatched speculatively in order, that supporting operands be available for the execution of the instructions, or tagged values substituted that will be available later, and that the functional units required for executing the instructions be available. The operation of the instruction decoder and the instruction cache is coordinated by a preset protocol which assures that the instructions are dispatched in ascending consecutive order and that blocks of instructions are efficiently fetched for decode and dispatch by the instruction decoder.
Abstract translation: 超标量微处理器在其每个读取，解码，执行和回写阶段对多个指令执行操作。 为了支持这种操作，超标量微处理器包括调度装置，其包括用于获取包括多个指令的指令块的指令高速缓存器以及将指令解码并分派到功能单元以执行的指令解码器。 指令解码器将调度标准应用于每个指令块的选择指令，并且调度满足调度准则的选定指令。 调度标准包括要求按顺序推测指令，支持操作数可用于执行指令，或替换为稍后可用的标记值，以及执行指令所需的功能单元可用。 指令解码器和指令高速缓存的操作由预设协议协调，该协议确保以上升的顺序分派指令，并且指令块被有效地提取以由指令解码器进行解码和分派。
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8.发明授权Processor configured to selectively cancel instructions from its pipeline responsive to a predicted-taken short forward branch instruction 失效处理器被配置为响应于预测的短前进分支指令来选择性地从其流水线中取消指令
公开(公告)号：US06256728B1
公开(公告)日：2001-07-03
申请号：US09110519
申请日：1998-07-06
Applicant: David B. Witt , William M. Johnson
Inventor： David B. Witt , William M. Johnson
IPC: G06F1500
CPC classification number: G06F12/0897 , G06F9/30021 , G06F9/30058 , G06F9/30069 , G06F9/3804 , G06F9/383 , G06F9/3838 , G06F9/3842 , G06F12/0862
Abstract: A processor is configured to detect a branch instruction have a forward branch target address within a predetermined range of the branch fetch address of the branch instruction. If the branch instruction is predicted taken, instead of canceling subsequent instructions and fetching the branch target address, the processor allows sequential fetching to continue and selectively cancels the sequential instructions which are not part of the predicted instruction sequence (i.e. the instructions between the predicted taken branch instruction and the target instruction identified by the forward branch target address). Instructions within the predicted instruction sequence which may already have been fetched prior to predicting the branch instruction taken may be retained within the pipeline of the processor, and yet subsequent instructions may be fetched.
Abstract translation: 处理器被配置为检测分支指令具有在分支指令的分支取出地址的预定范围内的前向分支目标地址。 如果预测了分支指令，则代替取消后续指令并取出分支目标地址，处理器允许连续提取继续并选择性地取消不是预测指令序列的一部分的顺序指令（即预测的采用指令之间的指令 分支指令和由转发目标地址识别的目标指令）。 在预测分支指令之前可能已经获取的预测指令序列内的指令可以保留在处理器的流水线内，并且可以获取随后的指令。
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9.发明授权Method for transferring data between a pair of caches configured to be accessed from different stages of an instruction processing pipeline 失效用于在配置成从指令处理流水线的不同阶段被访问的一对缓存之间传送数据的方法
公开(公告)号：US5903910A
公开(公告)日：1999-05-11
申请号：US561073
申请日：1995-11-20
Applicant: Thang M. Tran , Marty L. Pflum , David B. Witt , William M. Johnson
Inventor： Thang M. Tran , Marty L. Pflum , David B. Witt , William M. Johnson
CPC classification number: G06F9/30167 , G06F12/0875 , G06F9/30163 , G06F9/3824 , G06F9/3867
Abstract: A microprocessor including a pair of caches is provided. One of the pair of caches is accessed by stack-relative memory accesses from the decode stage of the instruction processing pipeline. The second of the pair of caches is accessed by memory accesses from the execute stage of the instruction processing pipeline. When a miss is detected in the first of the pair of caches, the stack-relative memory access which misses is conveyed to the execute stage of the instruction processing pipeline. When the stack-relative memory access accesses the second of the pair of caches, the cache line containing the access is transmitted to the first of the pair of caches for storage. The first of the pair of caches selects a victim line for replacement when the data is transferred from the second of the pair of caches. If the victim line has been modified while stored in the first cache, then the victim line is stored in a copyback buffer. A signal is asserted by the first cache to inform the second cache of the need to perform a victim line copyback. Requests from the execute stage of the instruction processing pipeline are stalled to allow the copyback to occur.
Abstract translation: 提供了包括一对高速缓存的微处理器。 一对缓存中的一个通过来自指令处理流水线的解码级的堆栈相对存储器访问进行访问。 该对高速缓存中的第二个由指令处理流水线的执行阶段的存储器访问访问。 当在一对高速缓存中的第一个中检测到未命中时，丢失的堆栈相对存储器访问被传送到指令处理流水线的执行阶段。 当堆栈相对存储器访问访问该对高速缓存中的第二个时，包含访问的高速缓存行被发送到该对高速缓存中的第一个用于存储。 一对缓存中的第一个在从一对缓存中的第二个数据传输数据时选择一个受害者行进行替换。 如果受害者行已被存储在第一个缓存中被修改，那么受害者行将被存储在一个副本缓冲区中。 一个信号由第一个缓存断言，通知第二个缓存是否需要执行受害线回拷。 来自指令处理流水线的执行阶段的请求被停止以允许发生回拷。
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10.发明授权High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations 失效高性能超标量微处理器包括通用重排序缓冲器和用于整数和浮点运算的公用寄存器文件
公开(公告)号：US5651125A
公开(公告)日：1997-07-22
申请号：US501243
申请日：1995-07-10
Applicant: David B. Witt , William M. Johnson
Inventor： David B. Witt , William M. Johnson
CPC classification number: G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30094 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/30174 , G06F9/3802 , G06F9/3806 , G06F9/3814 , G06F9/3822 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3885
Abstract: A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and the floating point unit also share a common reorder buffer, register file, branch prediction unit and load/store unit which all reside on the same main data processing bus. Instruction and data caches are coupled to a main memory via an internal address data bus which handles communications therebetween. An instruction decoder is coupled to the instruction cache and is capable of decoding multiple instructions per microprocessor cycle. Instructions are dispatched from the decoder in speculative order, issued out-of-order and completed out-of-order. Instructions are retired from the reorder buffer to the register file in-order. The functional units of the microprocessor desirably accommodate operands exhibiting multiple data widths. High performance and efficient use of the microprocessor die size are achieved by the sharing architecture of the disclosed superscalar microprocessor.
Abstract translation: 提供了一种超标量微处理器，其包括共享高性能主数据处理总线的整数功能单元和浮点功能单元。 整数单元和浮点单元还共享共同的重排序缓冲器，寄存器文件，分支预测单元和所有驻留在同一主数据处理总线上的加载/存储单元。 指令和数据高速缓存通过处理其间的通信的内部地址数据总线耦合到主存储器。 指令解码器耦合到指令高速缓存，并且能够每个微处理器周期解码多个指令。 指令以推测顺序从解码器发出，发出无序，完成无序。 指令从重新排序缓冲区中重新排序到寄存器文件。 微处理器的功能单元期望地容纳显示多个数据宽度的操作数。 通过所公开的超标量微处理器的共享架构来实现微处理器管芯尺寸的高性能和高效率的使用。
