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    Method for forming self-aligned dual salicide in CMOS technologies
    5.
    发明授权
    Method for forming self-aligned dual salicide in CMOS technologies 失效
    在CMOS技术中形成自对准双重自杀机的方法

    公开(公告)号：US07112481B2

    公开(公告)日：2006-09-26

    申请号：US11254929

    申请日：2005-10-20

    申请人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

    发明人： Sunfei Fang ,  Cyril Cabral, Jr. ,  Chester T. Dziobkowski ,  John J. Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James S. Nakos ,  An L. Steegen ,  Clement H. Wann

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

    摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

    摘要翻译： 一种制造互补金属氧化物半导体（CMOS）器件的方法，其中所述方法包括在用于容纳第一类型半导体器件的半导体衬底中形成第一阱区; 在所述半导体衬底中形成用于容纳第二类型半导体器件的第二阱区; 用掩模屏蔽第一类型半导体器件; 在所述第二类型半导体器件上沉积第一金属层; 在所述第二类型半导体器件上执行第一自对准硅化物形成; 去除面膜; 在所述第一和第二类型半导体器件上沉积第二金属层; 以及在所述第一类型半导体器件上执行第二自对准硅化物形成。 该方法仅需要一个图案级别，并且消除图案覆盖，因为它也简化了在不同设备上形成不同硅化物材料的工艺。

    Method and structure to form self-aligned selective-SOI
    8.
    发明授权
    Method and structure to form self-aligned selective-SOI 失效
    形成自对准选择性SOI的方法和结构

    公开(公告)号：US07482656B2

    公开(公告)日：2009-01-27

    申请号：US11421594

    申请日：2006-06-01

    申请人： Zhijiong Luo ,  Yung Fu Chong ,  Kevin K Dezfulian ,  Huilong Zhu ,  Judson R Holt

    发明人： Zhijiong Luo ,  Yung Fu Chong ,  Kevin K Dezfulian ,  Huilong Zhu ,  Judson R Holt

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66628 ,  H01L29/0653 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636

    摘要： Methods of forming a self-aligned, selective semiconductor on insulator (SOI) structure and a related structure are disclosed. In one embodiment, a method includes providing a substrate; forming a gate structure over a channel within the substrate; recessing a portion of the substrate adjacent the channel; forming an insulating layer on a bottom of the recessed portion; and forming a semiconductor material above the insulating layer. An upper surface of the semiconductor material may be sloped. A MOSFET structure may include a substrate; a channel; a source region and a drain region adjacent the channel; a gate structure above the channel and the substrate; a shallow trench isolation (STI) distal from the gate structure; a selectively laid insulating layer in at least one of the source region and the drain region; and an epitaxially grown semiconductor material above the selectively laid insulating layer.

    摘要翻译： 公开了形成自对准选择性半导体绝缘体（SOI）结构和相关结构的方法。 在一个实施例中，一种方法包括提供基底; 在所述衬底内的沟道上形成栅极结构; 使靠近通道的衬底的一部分凹陷; 在所述凹部的底部形成绝缘层; 以及在绝缘层上方形成半导体材料。 半导体材料的上表面可以是倾斜的。 MOSFET结构可以包括衬底; 一个渠道 与沟道相邻的源极区域和漏极区域; 在通道和衬底上方的栅极结构; 远离栅极结构的浅沟槽隔离（STI）; 在源极区域和漏极区域中的至少一个中选择性地铺设绝缘层; 以及在选择性铺设的绝缘层上方的外延生长的半导体材料。

    Method of fabricating a transistor structure
    9.
    发明授权
    Method of fabricating a transistor structure 有权
    制造晶体管结构的方法

    公开(公告)号：US07413961B2

    公开(公告)日：2008-08-19

    申请号：US11383952

    申请日：2006-05-17

    申请人： Yung Fu Chong ,  Kevin K. Dezfulian ,  Zhijiong Luo ,  Huilong Zhu

    发明人： Yung Fu Chong ,  Kevin K. Dezfulian ,  Zhijiong Luo ,  Huilong Zhu

    IPC分类号： H01L21/76

    CPC分类号： H01L29/7848 ,  H01L21/3065 ,  H01L21/31116 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

    摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. There is provided a method of forming a strained channel transistor structure on a substrate, comprising the steps of: forming a source stressor recess comprising a deep source recess and a source extension recess; forming a drain stressor recess comprising a deep drain recess and a drain extension recess; and subsequently forming a source stressor in said source stressor recess and a drain stressor in said drain stressor recess. The deep source/drain and source/drain extension stressors are formed by an uninterrupted etch process and an uninterrupted epitaxy process.

    摘要翻译： 本发明涉及半导体集成电路。 更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。 提供了一种在衬底上形成应变通道晶体管结构的方法，包括以下步骤：形成包括深源凹槽和源极延伸凹槽的源极应力器凹部; 形成包括深排水凹槽和排水延伸凹槽的排水应力槽; 并且随后在所述源应力器凹部中形成源应力器，以及在所述漏应力器凹部中形成漏应力器。 深源/漏极和源极/漏极延伸应力源通过不间断的蚀刻工艺和不间断的外延工艺形成。

    METHOD OF FABRICATING A TRANSISTOR STRUCTURE
    10.
    发明申请
    METHOD OF FABRICATING A TRANSISTOR STRUCTURE 有权
    制造晶体管结构的方法

    公开(公告)号：US20070269952A1

    公开(公告)日：2007-11-22

    申请号：US11383952

    申请日：2006-05-17

    申请人： Yung Fu Chong ,  Kevin K. Dezfulian ,  Zhijiong Luo ,  Huilong Zhu

    发明人： Yung Fu Chong ,  Kevin K. Dezfulian ,  Zhijiong Luo ,  Huilong Zhu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L21/3065 ,  H01L21/31116 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

    摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. There is provided a method of forming a strained channel transistor structure on a substrate, comprising the steps of: forming a source stressor recess comprising a deep source recess and a source extension recess; forming a drain stressor recess comprising a deep drain recess and a drain extension recess; and subsequently forming a source stressor in said source stressor recess and a drain stressor in said drain stressor recess. The deep source/drain and source/drain extension stressors are formed by an uninterrupted etch process and an uninterrupted epitaxy process.

    摘要翻译： 本发明涉及半导体集成电路。 更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。 提供了一种在衬底上形成应变通道晶体管结构的方法，包括以下步骤：形成包括深源凹槽和源极延伸凹槽的源极应力器凹部; 形成包括深排水凹槽和排水延伸凹槽的排水应力槽; 并且随后在所述源应力器凹部中形成源应力器，以及在所述漏应力器凹部中形成漏应力器。 深源/漏极和源极/漏极延伸应力源通过不间断的蚀刻工艺和不间断的外延工艺形成。