公开(公告)号：US20080117937A1

公开(公告)日：2008-05-22

申请号：US11603849

申请日：2006-11-22

申请人： Scott Firestone ,  Madhavi Kadiyala ,  Randall B. Baird ,  Manjunath S. Bangalore ,  Shantanu Sarkar

发明人： Scott Firestone ,  Madhavi Kadiyala ,  Randall B. Baird ,  Manjunath S. Bangalore ,  Shantanu Sarkar

IPC分类号： H04J3/06

CPC分类号： H04N21/4347 ,  H04N5/04 ,  H04N5/4401 ,  H04N21/23406 ,  H04N21/23412 ,  H04N21/2365 ,  H04N21/4305 ,  H04N21/4307 ,  H04N21/4341 ,  H04N21/44004 ,  H04N21/44012 ,  H04N21/64723 ,  H04N21/8547

摘要： In one embodiment, a system includes a video mixer coupled with an audio mixer for exchange of information that includes a first set of delay values respecting input audio streams received by the audio mixer from a plurality of source endpoints, and output audio streams sent from the audio mixer to a plurality of destination endpoints. The information further including a second set of delay values respecting the corresponding input video streams. The audio mixer calculates end-to-end video delays, and the video mixer calculates end-to-end audio delays. The audio mixer delays the output audio streams to equalize the end-to-end audio and video delays in the event that the end-to-end audio delays are less than the end-to-end video delays, and the video mixer delays the output video streams to equalize the end-to-end audio and video delays in the event that the end-to-end video delays are less than the end-to-end audio delays.

摘要翻译： 在一个实施例中，系统包括与音频混合器耦合的视频混合器，用于交换信息，所述信息包括与多个源端点相关的音频混合器接收的输入音频流的第一组延迟值，以及输出从 音频混合器到多个目的地端点。 所述信息还包括相对于相应的输入视频流的第二组延迟值。 音频混合器计算端到端视频延迟，视频混合器可以计算端到端的音频延迟。 在端到端音频延迟小于端到端视频延迟的情况下，音频混合器延迟输出音频流以均衡端到端音频和视频延迟，并且视频混频器延迟 输出视频流以在终端到终端视频延迟小于端到端音频延迟的情况下均衡端对端音频和视频延迟。

公开(公告)号：US07693190B2

公开(公告)日：2010-04-06

申请号：US11603849

申请日：2006-11-22

申请人： Scott Firestone ,  Madhavi Kadiyala ,  Randall B. Baird ,  Manjunath S. Bangalore ,  Shantanu Sarkar

发明人： Scott Firestone ,  Madhavi Kadiyala ,  Randall B. Baird ,  Manjunath S. Bangalore ,  Shantanu Sarkar

IPC分类号： H04J3/06

CPC分类号： H04N21/4347 ,  H04N5/04 ,  H04N5/4401 ,  H04N21/23406 ,  H04N21/23412 ,  H04N21/2365 ,  H04N21/4305 ,  H04N21/4307 ,  H04N21/4341 ,  H04N21/44004 ,  H04N21/44012 ,  H04N21/64723 ,  H04N21/8547

摘要： In one embodiment, a system includes a video mixer coupled with an audio mixer for exchange of information that includes a first set of delay values respecting input audio streams received by the audio mixer from a plurality of source endpoints, and output audio streams sent from the audio mixer to a plurality of destination endpoints. The information further including a second set of delay values respecting the corresponding input video streams. The audio mixer calculates end-to-end video delays, and the video mixer calculates end-to-end audio delays. The audio mixer delays the output audio streams to equalize the end-to-end audio and video delays in the event that the end-to-end audio delays are less than the end-to-end video delays, and the video mixer delays the output video streams to equalize the end-to-end audio and video delays in the event that the end-to-end video delays are less than the end-to-end audio delays.

摘要翻译： 在一个实施例中，系统包括与音频混合器耦合的视频混合器，用于交换信息，所述信息包括与多个源端点相关的音频混合器接收的输入音频流的第一组延迟值，以及输出从 音频混合器到多个目的地端点。 所述信息还包括相对于相应的输入视频流的第二组延迟值。 音频混合器计算端到端视频延迟，视频混合器可以计算端到端的音频延迟。 在端到端音频延迟小于端到端视频延迟的情况下，音频混合器延迟输出音频流以均衡端到端音频和视频延迟，并且视频混频器延迟 输出视频流以在终端到终端视频延迟小于端到端音频延迟的情况下均衡端对端音频和视频延迟。

公开(公告)号：US07499446B1

公开(公告)日：2009-03-03

申请号：US10135223

申请日：2002-04-29

申请人： Dayin Gou ,  Madhavi Kadiyala ,  Xiaomei Liu

发明人： Dayin Gou ,  Madhavi Kadiyala ,  Xiaomei Liu

IPC分类号： H04L12/28

CPC分类号： H04L12/2801 ,  H04L47/10 ,  H04L47/225 ,  H04L47/2416 ,  H04L47/2441 ,  H04L47/283 ,  H04L47/564 ,  H04L65/608 ,  H04L65/80 ,  H04L69/28

摘要： The present invention addresses the issue of jitter and clock drifting in streaming media applications. The present invention utilizes the Real Time Transaction Protocol (RTP) to embed MPEG packets within RTP packets in a Multiple Program Transport Stream (MPTS). Each MPEG packet in an MPTS stream is tagged at a gateway with: an arrival timestamp, a per-flow index and internal index to identify where the packet resides in an RTP packet and within a stream. After demultiplexing, this information is utilized in conjunction with the sending timestamp of each RTP packet to create a sending time for each MPEG packet to aid in the reduction of jitter and clock drifting.

摘要翻译： 本发明解决了流媒体应用中抖动和时钟漂移的问题。 本发明利用实时事务协议（RTP）将多个节目传输流（MPTS）中的RTP分组中的MPEG分组嵌入到RTP分组中。 MPTS流中的每个MPEG分组在网关处被标记为：到达时间戳，每流索引和内部索引，以标识分组驻留在RTP分组中以及流内的哪里。 解复用后，该信息与每个RTP分组的发送时间戳一起使用，以创建每个MPEG分组的发送时间，以帮助减少抖动和时钟漂移。

公开(公告)号：US20120185820A1

公开(公告)日：2012-07-19

申请号：US13008901

申请日：2011-01-19

申请人： Suresh Kadiyala ,  Madhavi Kadiyala ,  Sanjay Banerjee ,  Satish Padmanabhan ,  James Player

发明人： Suresh Kadiyala ,  Madhavi Kadiyala ,  Sanjay Banerjee ,  Satish Padmanabhan ,  James Player

IPC分类号： G06F9/44

CPC分类号： G06F8/37

摘要： Systems and methods are disclosed to automatically generate software development tools for an automatically generated processor architecture by: receiving a description of a target processor; automatically generating a target compiler using a compiler generator; automatically generating a target assembler using an assembler generator; automatically generating a target linker using a linker generator; automatically generating a target simulator using a simulator generator; automatically generating a target profiler using a profiler generator; iteratively generating a new processor architecture by changing one or more parameters of the processor architecture until all user constraints or requirements are met using the generated target compiler, assembler, linker, simulator, and profiler; for each new processor architecture regenerating the target compiler, assembler, linker, simulator, profiler for the new processor architecture; and synthesizing an optimal generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

摘要翻译： 公开了系统和方法，通过以下方式自动生成用于自动生成的处理器架构的软件开发工具：接收目标处理器的描述; 使用编译器生成器自动生成目标编译器; 使用汇编器生成器自动生成目标汇编程序; 使用链接器生成器自动生成目标链接器; 使用模拟器发生器自动生成目标模拟器; 使用分析器生成器自动生成目标分析器; 通过改变处理器架构的一个或多个参数来迭代地生成新的处理器架构，直到使用生成的目标编译器，汇编器，链接器，模拟器和分析器来满足所有用户约束或需求为止; 为每个新的处理器架构重新生成新的处理器架构的目标编译器，汇编器，链接器，模拟器，分析器; 以及将最佳生成的处理器架构合成到用于半导体制造的定制集成电路的计算机可读描述中。