公开(公告)号：US09281037B2

公开(公告)日：2016-03-08

申请号：US12776154

申请日：2010-05-07

申请人： Scott Smith ,  Duc Ho ,  J. Thomas Pawlowski

发明人： Scott Smith ,  Duc Ho ,  J. Thomas Pawlowski

IPC分类号： G11C5/14 ,  G11C8/00 ,  G11C8/18 ,  G11C7/10 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4096

CPC分类号： G11C11/4076 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1066 ,  G11C7/1072 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.

摘要翻译： 公开了系统，装置和方法。 在一种这样的方法的实施例中，一种对接收到的命令信号进行解码的方法，该方法包括将接收的命令信号与在时钟信号的第一时钟沿提供给存储器地址节点的信号相结合地解码，以产生多个存储器 控制信号。 接收到的命令信号与在时钟信号的第一时钟沿提供给存储器地址节点的信号相结合表示存储器命令。 此外，在时钟信号的第二时钟沿提供给存储器地址节点的信号不与所接收的命令信号组合解码。 存储器命令可以是减少功率命令和/或无操作命令。

公开(公告)号：US20090067277A1

公开(公告)日：2009-03-12

申请号：US11899738

申请日：2007-09-06

申请人： Scott Smith ,  Duc Ho ,  J. Thomas Pawlowski

发明人： Scott Smith ,  Duc Ho ,  J. Thomas Pawlowski

IPC分类号： G11C8/18

CPC分类号： G11C11/4076 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1066 ,  G11C7/1072 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to decode received write enable, row address strobe and column address strobe signals to place the memory device in at least one reduced power state despite the absence of either a clock enable signal or a chip select signal. The command decoder performs this function by decoding the write enable, row address strobe and column address strobe signals in combination with at least one address signal received by the memory device. The command decoder can also decode a no operation command, which differs from the at least one reduced power state by only the state of the write enable signal. As a result, when the at least one reduced power state is terminated by a transition of the write enable signal, the memory device automatically transitions to a no operation mode.

摘要翻译： 公开了系统，装置和方法。 在一个这样的设备的实施例中，存储器件的实施例包括命令解码器，其可操作以解码所接收的写入使能，行地址选通和列地址选通信号，以将存储器件置于至少一个降低功率状态，尽管不存在 时钟使能信号或芯片选择信号。 命令解码器通过结合存储器件接收的至少一个地址信号来解码写使能，行地址选通和列地址选通信号来执行该功能。 命令解码器还可以仅通过写使能信号的状态来解码不同于至少一个降低功率状态的无操作命令。 结果，当通过写使能信号的转变来终止至少一个降低功率状态时，存储器件自动转换到无操作模式。

公开(公告)号：US20100214864A1

公开(公告)日：2010-08-26

申请号：US12776154

申请日：2010-05-07

申请人： Scott Smith ,  Duc Ho ,  J. Thomas Pawlowski

发明人： Scott Smith ,  Duc Ho ,  J. Thomas Pawlowski

IPC分类号： G11C8/10 ,  G11C7/00 ,  G11C5/14

CPC分类号： G11C11/4076 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1066 ,  G11C7/1072 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to decode received write enable, row address strobe and column address strobe signals to place the memory device in at least one reduced power state despite the absence of either a clock enable signal or a chip select signal. The command decoder performs this function by decoding the write enable, row address strobe and column address strobe signals in combination with at least one address signal received by the memory device. The command decoder can also decode a no operation command, which differs from the at least one reduced power state by only the state of the write enable signal. As a result, when the at least one reduced power state is terminated by a transition of the write enable signal, the memory device automatically transitions to a no operation mode.

摘要翻译： 公开了系统，装置和方法。 在一个这样的设备的实施例中，存储器件的实施例包括命令解码器，其可操作以解码所接收的写入使能，行地址选通和列地址选通信号，以将存储器件置于至少一个降低功率状态，尽管不存在 时钟使能信号或芯片选择信号。 命令解码器通过结合存储器件接收的至少一个地址信号来解码写使能，行地址选通和列地址选通信号来执行该功能。 命令解码器还可以仅通过写使能信号的状态来解码不同于至少一个降低功率状态的无操作命令。 结果，当通过写使能信号的转变来终止至少一个降低功率状态时，存储器件自动转换到无操作模式。

公开(公告)号：US07729191B2

公开(公告)日：2010-06-01

申请号：US11899738

申请日：2007-09-06

申请人： Scott Smith ,  Duc Ho ,  J. Thomas Pawlowski

发明人： Scott Smith ,  Duc Ho ,  J. Thomas Pawlowski

IPC分类号： G11C5/14 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4076 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1066 ,  G11C7/1072 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to decode received write enable, row address strobe and column address strobe signals to place the memory device in at least one reduced power state despite the absence of either a clock enable signal or a chip select signal. The command decoder performs this function by decoding the write enable, row address strobe and column address strobe signals in combination with at least one address signal received by the memory device. The command decoder can also decode a no operation command, which differs from the at least one reduced power state by only the state of the write enable signal. As a result, when the at least one reduced power state is terminated by a transition of the write enable signal, the memory device automatically transitions to a no operation mode.

摘要翻译： 公开了系统，装置和方法。 在一个这样的设备的实施例中，存储器件的实施例包括命令解码器，其可操作以解码所接收的写入使能，行地址选通和列地址选通信号，以将存储器件置于至少一个降低功率状态，尽管不存在 时钟使能信号或芯片选择信号。 命令解码器通过结合存储器件接收的至少一个地址信号来解码写使能，行地址选通和列地址选通信号来执行该功能。 命令解码器还可以仅通过写使能信号的状态来解码不同于至少一个降低功率状态的无操作命令。 结果，当通过写使能信号的转变来终止至少一个降低功率状态时，存储器件自动转换到无操作模式。

公开(公告)号：US09389833B2

公开(公告)日：2016-07-12

申请号：US13538714

申请日：2012-06-29

申请人： J. Thomas Pawlowski

发明人： J. Thomas Pawlowski

IPC分类号： G06F1/32 ,  G06F7/02

CPC分类号： G06F1/3287 ,  G06F1/3203 ,  G06F1/3206 ,  G06F7/02 ,  G06F2207/025 ,  G06N5/047

摘要： A device includes a pattern-recognition processor. The pattern recognition processor includes blocks, such that each of the blocks include a plurality of feature cells configured to analyze at least a portion of data to be analyzed and to selectively provide a result of the analysis. The pattern recognition processor also includes block deactivation logic configured to dynamically power-down the block.

摘要翻译： 一种设备包括模式识别处理器。 模式识别处理器包括块，使得每个块包括被配置成分析待分析的数据的至少一部分的多个特征单元并且选择性地提供分析的结果。 模式识别处理器还包括被配置为动态地关闭该块的块去激活逻辑。

公开(公告)号：US08769213B2

公开(公告)日：2014-07-01

申请号：US12546258

申请日：2009-08-24

申请人： Dan Skinner ,  J. Thomas Pawlowski

发明人： Dan Skinner ,  J. Thomas Pawlowski

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F13/1631 ,  G06F13/16 ,  G06F13/1636 ,  G11C7/1075 ,  G11C8/16 ,  Y02D10/14

摘要： Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications.

摘要翻译： 具有用于在端口之间传递命令的附加控制总线的多端口存储器具有可被配置为响应从外部控制总线接收的命令或从附加控制总线接收的命令的各个端口。 这有助于端口的各种组合来改变存储器的带宽或延迟，以便于针对不同的应用定制性能特征。

公开(公告)号：US08413007B2

公开(公告)日：2013-04-02

申请号：US13026833

申请日：2011-02-14

申请人： J. Thomas Pawlowski ,  John Schreck

发明人： J. Thomas Pawlowski ,  John Schreck

IPC分类号： H03M13/00

CPC分类号： H03M13/151 ,  G06F11/10 ,  G06F11/1044 ,  G11C7/1006 ,  G11C11/406 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/4062

摘要： A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.

摘要翻译： DRAM装置包括ECC生成器/检查器，其生成与存储在DRAM装置中的数据对应的ECC校正子。 DRAM设备还包括ECC控制器，其使ECC校验子存储在DRAM设备中。 当存储相应的ECC综合征时，ECC控制器还使得具有第一值的标志位被存储在DRAM设备中。 每当相应的数据位被修改时，ECC控制器将标志位改变为第二值，这表示存储的校正符不再对应于存储的数据。 在这种情况下，ECC控制器产生并存储新的ECC校验子，并且相应的标志位被复位到第一个值。 可以在减少功率刷新期间以这种方式检查标志位，以确保所存储的校正子对应于所存储的数据。

公开(公告)号：US08359517B2

公开(公告)日：2013-01-22

申请号：US13026030

申请日：2011-02-11

申请人： J. Thomas Pawlowski

发明人： J. Thomas Pawlowski

IPC分类号： H03M13/00 ,  G11C29/00

CPC分类号： G06F11/1076 ,  G06F11/1008 ,  G06F11/1044 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/40622 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/4062 ,  G11C2211/4067

摘要： A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells.

摘要翻译： DRAM存储器件包括几组存储器单元，每个存储单元被分成第一组和第二组存储器单元。 可以以相对较慢的速率刷新第一组中的存储器单元以减少DRAM器件消耗的功率。 DRAM设备中的错误检查和校正电路校正由相对较慢的刷新率引起的第一组存储器单元中的任何数据保留错误。 第二组中的存储单元以正常速率刷新，速度足够快，不会发生数据保留错误。 可以对DRAM装置中的模式寄存器进行编程，以选择第二组存储器单元的大小。

公开(公告)号：US08281395B2

公开(公告)日：2012-10-02

申请号：US12350132

申请日：2009-01-07

申请人： J. Thomas Pawlowski

发明人： J. Thomas Pawlowski

IPC分类号： H04L29/06 ,  G06F11/00 ,  G06F15/173 ,  G06F7/02 ,  G06F13/40

CPC分类号： G06N5/025 ,  G06F7/02 ,  G06F2207/025 ,  G06K9/62

摘要： Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor. The pattern-recognition processor may include a matching-data reporting module, which may have a buffer and a match event table. The buffer may be coupled to a data stream and configured to store at least part of the data stream, and the match event table may be configured to store data indicative of a buffer location corresponding with a start of a search criterion being satisfied.

摘要翻译： 公开了方法和装置，其中包括模式识别处理器的装置。 模式识别处理器可以包括匹配数据报告模块，其可以具有缓冲器和匹配事件表。 缓冲器可以耦合到数据流并且被配置为存储数据流的至少一部分，并且匹配事件表可以被配置为存储指示与满足搜索条件的开始相对应的缓冲器位置的数据。

公开(公告)号：US20110138251A1

公开(公告)日：2011-06-09

申请号：US13026030

申请日：2011-02-11

申请人： J. Thomas Pawlowski

发明人： J. Thomas Pawlowski

IPC分类号： H03M13/05 ,  G11C11/402 ,  G06F11/10

CPC分类号： G06F11/1076 ,  G06F11/1008 ,  G06F11/1044 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/40622 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/4062 ,  G11C2211/4067

摘要： A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells.

摘要翻译： DRAM存储器件包括几组存储器单元，每个存储单元被分成第一组和第二组存储器单元。 可以以相对较慢的速率刷新第一组中的存储器单元以减少DRAM器件消耗的功率。 DRAM设备中的错误检查和校正电路校正由相对较慢的刷新率引起的第一组存储器单元中的任何数据保留错误。 第二组中的存储单元以正常速率刷新，速度足够快，不会发生数据保留错误。 可以对DRAM装置中的模式寄存器进行编程，以选择第二组存储器单元的大小。