公开(公告)号：US08749001B2

公开(公告)日：2014-06-10

申请号：US13228989

申请日：2011-09-09

申请人： Terunao Hanaoka ,  Akinori Shindo ,  Yasuo Yamasaki ,  Seiichi Chiba ,  Toshiyuki Enta ,  Shuji Kojima

发明人： Terunao Hanaoka ,  Akinori Shindo ,  Yasuo Yamasaki ,  Seiichi Chiba ,  Toshiyuki Enta ,  Shuji Kojima

IPC分类号： H01L21/00 ,  G01P15/097

CPC分类号： H01L27/0207 ,  G01C19/5769 ,  G01C19/5783

摘要： An electronic component includes: a semiconductor element including a circuit; a vibration element; a first electrode arranged on a first surface of the semiconductor element and connected to the circuit and the vibration element arranged on the first surface side; a second electrode arranged on the first surface; a first wiring board including a first wire connected to the second electrode; and a second wiring board including a second wire to which the first wire is connected. At least a part of an inner side region of an outer contour of the vibration element is arranged to overlap the second electrode in plan view facing the first surface.

摘要翻译： 电子部件包括：包括电路的半导体元件; 振动元件 布置在所述半导体元件的第一表面上并连接到所述电路的第一电极和布置在所述第一表面侧上的所述振动元件; 布置在所述第一表面上的第二电极; 第一布线板，包括连接到第二电极的第一线; 以及第二配线基板，包括连接有第一配线的第二配线。 振动元件的外轮廓的内侧区域的至少一部分布置成在面向第一表面的平面图中与第二电极重叠。

公开(公告)号：US08631701B2

公开(公告)日：2014-01-21

申请号：US13225869

申请日：2011-09-06

申请人： Seiichi Chiba ,  Shuji Kojima ,  Toshiyuki Enta ,  Akinori Shindo ,  Terunao Hanaoka ,  Yasuo Yamasaki

发明人： Seiichi Chiba ,  Shuji Kojima ,  Toshiyuki Enta ,  Akinori Shindo ,  Terunao Hanaoka ,  Yasuo Yamasaki

IPC分类号： G01C19/56

CPC分类号： G01P15/097 ,  B81B7/0006 ,  G01C19/5783 ,  H01L2224/48091 ,  H01L2924/00014

摘要： A sensor device includes a first electrode disposed on active surface side of a silicon substrate, an external connecting terminal electrically connected to the first electrode, at least one stress relaxation layer disposed between the silicon substrate and the external connecting terminal, a connecting terminal disposed on the active surface side of the silicon substrate, and a vibration gyro element having weight sections as mass adjustment sections, the vibration gyro element is held by the silicon substrate due to connection between the connection electrode and the external connecting terminal, and a meltage protection layer formed in an area where the stress relaxation layer and the mass adjustment section overlap each other in a plan view is provided.

摘要翻译： 传感器装置包括设置在硅衬底的有源表面侧的第一电极，与第一电极电连接的外部连接端子，设置在硅衬底和外部连接端子之间的至少一个应力松弛层， 硅衬底的有源表面侧和具有作为质量调节部分的重量部分的振动陀螺元件，由于连接电极和外部连接端子之间的连接，振动陀螺元件由硅衬底保持，并且熔融保护层 形成在应力松弛层和质量调节部在平面图中彼此重叠的区域中。

公开(公告)号：US07649260B2

公开(公告)日：2010-01-19

申请号：US11424891

申请日：2006-06-19

申请人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

发明人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

IPC分类号： H01L23/532

CPC分类号： H01L24/05 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device including: a semiconductor layer including an active region and an isolation region provided around the active region; an element formed in the active region; an interlayer dielectric formed above the semiconductor layer; and an electrode pad formed above the interlayer dielectric and having a rectangular planar shape having a short side and a long side, the electrode pad at least partially covering the element when viewed from a top side, and the semiconductor layer positioned in a specific range outward from a line extending vertically downward from the short side of the electrode pad being a forbidden region.

摘要翻译： 一种半导体器件，包括：半导体层，包括有源区和设置在有源区周围的隔离区; 在活性区域中形成的元素; 形成在所述半导体层上方的层间电介质; 以及形成在所述层间电介质的上方并具有短边和长边的矩形平面形状的电极焊盘，所述电极焊盘从顶侧观察时至少部分地覆盖所述元件，并且所述半导体层位于特定范围外侧 从作为禁止区域的电极焊盘的短边垂直向下延伸的线。

公开(公告)号：US07598569B2

公开(公告)日：2009-10-06

申请号：US11429581

申请日：2006-05-05

申请人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

发明人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

IPC分类号： H01L29/78

CPC分类号： H01L21/823462 ,  H01L27/088 ,  H01L29/1037 ,  H01L29/1041 ,  H01L29/42368 ,  H01L29/78 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/013

摘要： A semiconductor device including: a semiconductor layer; a transistor formed in the semiconductor layer and including a gate insulating layer and a gate electrode, the transistor being a high voltage transistor in which an insulating layer having a thickness greater than the thickness of the gate insulating layer is formed under an end portion of the gate electrode; an interlayer dielectric formed above the transistor; and an electrode pad formed above the interlayer dielectric and positioned over at least part of the gate electrode when viewed from a top side.

摘要翻译： 一种半导体器件，包括：半导体层; 形成在所述半导体层中并且包括栅极绝缘层和栅电极的晶体管，所述晶体管是高压晶体管，其中在所述栅极绝缘层的端部的下方形成有厚度大于所述栅极绝缘层的厚度的绝缘层 栅电极 形成在晶体管上方的层间电介质; 以及形成在所述层间电介质上方并且位于所述栅电极的至少一部分上方的电极焊盘，当从顶侧观察时。

公开(公告)号：US20080142906A1

公开(公告)日：2008-06-19

申请号：US12070320

申请日：2008-02-15

申请人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

发明人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

IPC分类号： H01L27/088

CPC分类号： H01L24/13 ,  H01L21/823475 ,  H01L21/823481 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/013

摘要： A semiconductor device comprising: a semiconductor layer including an element formation region, and first and second spaced apart isolation regions; an element in the element formation region; an interlayer dielectric layer above the semiconductor layer; an electrode pad above the interlayer dielectric layer; a passivation layer above the electrode pad and having an opening which exposes part of the electrode pad; and a bump in the opening and covering part of the element when viewed from a top side, the bump including a first edge when viewed from the top side, the first isolation region being formed in a first region, the first region including a first specific distance outward from a first line directly below the first edge of the bump, the second isolation region being formed in a second region, the second region including a second specific distance inward from the first line.

摘要翻译： 一种半导体器件，包括：半导体层，包括元件形成区域，以及第一和第二间隔开的隔离区域; 元素形成区域中的元素; 半导体层上方的层间电介质层; 层间介电层上方的电极焊盘; 在所述电极焊盘上方具有暴露所述电极焊盘的一部分的开口的钝化层; 以及当从顶侧观察时所述元件的开口和覆盖部分中的凸块，所述凸块包括从顶侧观察时的第一边缘，所述第一隔离区域形成在第一区域中，所述第一区域包括第一特定 从凸起的第一边缘正下方的第一线向外延伸，第二隔离区域形成在第二区域中，第二区域包括从第一线向内的第二特定距离。

公开(公告)号：US20060237842A1

公开(公告)日：2006-10-26

申请号：US11453063

申请日：2006-06-15

申请人： Akinori Shindo

发明人： Akinori Shindo

IPC分类号： H01L23/48

CPC分类号： H01L24/12 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

摘要： Making the relative size of the surface area of a bump electrode at a portion in contact with an under electrode larger than the surface area of a base of a hole increases the contact surface area between the lower surface of the bump electrode and a polyimide layer. As a result, effect by the polyimide layer to mitigate the impact loads applied during bonding greatly increases. The impact loads applied during bonding can also be mitigated by using a material for the conductive layer that is as flexible as, or even more flexible than, the material of the bump electrode. It is therefore possible to reduce cracks in semiconductor chips or the like directly under the bump electrode more efficiently.

公开(公告)号：US07777334B2

公开(公告)日：2010-08-17

申请号：US12070320

申请日：2008-02-15

申请人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

发明人： Akinori Shindo ,  Masatoshi Tagaki ,  Hideaki Kurita

IPC分类号： H01L23/485

CPC分类号： H01L24/13 ,  H01L21/823475 ,  H01L21/823481 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/013

摘要： A semiconductor device comprising: a semiconductor layer including an element formation region, and first and second spaced apart isolation regions; an element in the element formation region; an interlayer dielectric layer above the semiconductor layer; an electrode pad above the interlayer dielectric layer; a passivation layer above the electrode pad and having an opening which exposes part of the electrode pad; and a bump in the opening and covering part of the element when viewed from a top side, the bump including a first edge when viewed from the top side, the first isolation region being formed in a first region, the first region including a first specific distance outward from a first line directly below the first edge of the bump, the second isolation region being formed in a second region, the second region including a second specific distance inward from the first line.

摘要翻译： 一种半导体器件，包括：半导体层，包括元件形成区域，以及第一和第二间隔开的隔离区域; 元素形成区域中的元素; 半导体层上方的层间电介质层; 层间介电层上方的电极焊盘; 在所述电极焊盘上方具有暴露所述电极焊盘的一部分的开口的钝化层; 以及当从顶侧观察时所述元件的开口和覆盖部分中的凸块，所述凸块包括从顶侧观察时的第一边缘，所述第一隔离区域形成在第一区域中，所述第一区域包括第一特定 从凸起的第一边缘正下方的第一线向外延伸，第二隔离区域形成在第二区域中，第二区域包括从第一线向内的第二特定距离。

公开(公告)号：US20070023825A1

公开(公告)日：2007-02-01

申请号：US11478486

申请日：2006-06-29

申请人： Akinori Shindo

发明人： Akinori Shindo

IPC分类号： H01L29/76

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/06 ,  H01L29/78 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/19043

摘要： A semiconductor device having: a semiconductor layer; an interlayer dielectric formed on the semiconductor layer; a buffer layer formed on the interlayer dielectric; and an electrode pad formed on the interlayer dielectric, the buffer layer being formed to be covered by an edge portion of at least part of the electrode pad when viewed from a top side.

摘要翻译： 一种半导体器件，具有：半导体层; 形成在所述半导体层上的层间电介质; 形成在层间电介质上的缓冲层; 以及形成在所述层间电介质上的电极焊盘，所述缓冲层形成为当从顶侧观察时被所述电极焊盘的至少一部分的边缘部分覆盖。

公开(公告)号：US20060273464A1

公开(公告)日：2006-12-07

申请号：US11402324

申请日：2006-04-11

申请人： Akinori Shindo

发明人： Akinori Shindo

IPC分类号： H01L23/48

CPC分类号： H01L24/02 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/19043

摘要： A semiconductor device comprises: an insulation layer located on or above a semiconductor element; a conductive pad formed on the insulation film; and a first opening pattern formed on the conductive pad.

公开(公告)号：US20050116340A1

公开(公告)日：2005-06-02

申请号：US10958274

申请日：2004-10-06

申请人： Akinori Shindo

发明人： Akinori Shindo

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/44 ,  H01L21/60 ,  H01L23/00 ,  H01L23/485 ,  H01L23/522 ,  H01L31/12

CPC分类号： H01L24/12 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

摘要： Making the relative size of the surface area of a bump electrode at a portion in contact with an under electrode larger than the surface area of a base of a hole increases the contact surface area between the lower surface of the bump electrode and a polyimide layer. As a result, effect by the polyimide layer to mitigate the impact loads applied during bonding greatly increases. The impact loads applied during bonding can also be mitigated by using a material for the conductive layer that is as flexible as, or even more flexible than, the material of the bump electrode. It is therefore possible to reduce cracks in semiconductor chips or the like directly under the bump electrode more efficiently.

摘要翻译： 使凸块电极的表面积相对于与大于孔的基底的表面积的下电极接触的部分的相对尺寸增加凸块电极的下表面与聚酰亚胺层之间的接触表面积。 结果，通过聚酰亚胺层的作用来减轻在接合期间施加的冲击载荷大大增加。 也可以通过使用与凸块电极的材料一样柔软或甚至更柔性的导电层的材料来减轻接合期间施加的冲击载荷。 因此，可以更有效地减少凸起电极下方的半导体芯片等的龟裂。