Automatic generation of streaming data interface circuit
    1.
    发明授权
    Automatic generation of streaming data interface circuit 有权
    自动生成流数据接口电路

    公开(公告)号:US07603492B2

    公开(公告)日:2009-10-13

    申请号:US11231171

    申请日:2005-09-20

    IPC分类号: G06F13/00 G06F13/12 G06F15/00

    摘要: A streaming data interface device (700) of a streaming processing system (200) is automatically generated by selecting a set of circuit parameters (610) consistent with a set of circuit constraints and generating (612, 614) a representation of a candidate memory interface device based upon a set of stream descriptors. The candidate streaming data interface device is evaluated (616) with respect to one or more quality metrics and the representation of the candidate streaming processor circuit is output (622) if the candidate memory interface device satisfies a set of processing system constraints and is better in at least one of the one or more quality metrics than other candidate memory interface devices.

    摘要翻译: 通过选择与一组电路约束一致的一组电路参数(610)来自动生成流处理系统(200)的流数据接口设备(700),并生成(612,614)候选存储器接口的表示 设备基于一组流描述符。 对于一个或多个质量度量评估候选流数据接口设备(616),如果候选存储器接口设备满足一组处理系统约束并且更好地输出候选流处理器电路的表示(622) 所述一个或多个质量度量中的至少一个与其它候选存储器接口设备相比。

    Automatic generation of a streaming processor circuit
    2.
    发明授权
    Automatic generation of a streaming processor circuit 有权
    自动生成流处理器电路

    公开(公告)号:US07305649B2

    公开(公告)日:2007-12-04

    申请号:US11109915

    申请日:2005-04-20

    IPC分类号: G06F17/50 G06F15/00 H03K19/00

    CPC分类号: G06F17/5045

    摘要: A streaming processor circuit of a processing system is automatically generated by selecting a set of circuit parameters consistent with a set of circuit constraints and generating a representation of a candidate streaming processor circuit based upon the set of circuit parameters to execute one or more iterations of a computation specified by a streaming data flow graph. The candidate streaming processor circuit is evaluated with respect to one or more quality metrics and the representation of the candidate streaming processor circuit is output if the candidate streaming processor circuit satisfies a set of processing system constraints and is better in at least one of the one or more quality metrics than other candidate streaming processor circuits.

    摘要翻译: 通过选择与一组电路约束一致的电路参数集合来自动生成处理系统的流处理器电路,并且基于该组电路参数生成候选流处理器电路的表示,以执行一个或多个迭代 由流数据流图指定的计算。 候选流处理器电路相对于一个或多个质量度量进行评估,并且如果候选流处理器电路满足一组处理系统约束并且在一个或多个处理器电路中的至少一个中更好地输出候选流处理器电路的表示, 比其他候选流处理器电路更多的质量指标。

    Method and Apparatus for Configuring Buffers for Streaming Data Transfer
    3.
    发明申请
    Method and Apparatus for Configuring Buffers for Streaming Data Transfer 失效
    用于配置数据流传输缓冲器的方法和装置

    公开(公告)号:US20080244152A1

    公开(公告)日:2008-10-02

    申请号:US11694523

    申请日:2007-03-30

    IPC分类号: G06F12/00

    CPC分类号: G06F12/0646

    摘要: A specification of a configurable processor is generated by generating (1) specifications of first and second stream memory interfaces to be operable to access data in accordance with first and second stream descriptors, and (2) a specification of an interim data storage device (buffer) to be accessed by the first and second stream memory interfaces and to be operable to receive data from a first computational module via the first stream memory interface and to transfer data to a second computational module via the second stream memory interface. The specifications are output and may be used to configure a configurable processor.

    摘要翻译: 通过生成(1)第一和第二流存储器接口的规格来生成可配置处理器的规范,以便根据第一和第二流描述符访问数据,以及(2)临时数据存储设备(缓冲器) )被第一和第二流存储器接口访问,并且可操作以经由第一流存储器接口从第一计算模块接收数据,并经由第二流存储器接口将数据传送到第二计算模块。 输出规格,可用于配置可配置的处理器。

    AUTOMATED CONFIGURATION OF A PROCESSING SYSTEM USING DECOUPLED MEMORY ACCESS AND COMPUTATION
    4.
    发明申请
    AUTOMATED CONFIGURATION OF A PROCESSING SYSTEM USING DECOUPLED MEMORY ACCESS AND COMPUTATION 审中-公开
    使用解密存储器访问和计算的处理系统的自动配置

    公开(公告)号:US20080120497A1

    公开(公告)日:2008-05-22

    申请号:US11561486

    申请日:2006-11-20

    IPC分类号: G06F9/00

    CPC分类号: G06F9/3877 G06F8/433

    摘要: A method and system for automatic configuration of processor hardware from an application program that has stream descriptor definitions, descriptive of memory access locations, data access thread definitions having a stream descriptor and a data channel source or sink as parameters, and computation thread definitions having a function pointer, a data channel source and a data channel sink as parameters. The application program is compiled to produce a description of the data flow between the threads as specified in the application program. The hardware is configured to have streaming memory interface devices operable to access a memory in accordance with the stream descriptor definitions, data path devices operable to process data in accordance with the computation thread definitions and data channels operable to connect the data path devices and streaming memory interface devices in accordance with the description of the data flow.

    摘要翻译: 一种用于从具有流描述符定义,描述存储器访问位置,具有流描述符的数据访问线程定义和数据通道源或宿作为参数的应用程序自动配置处理器硬件的方法和系统,以及具有 功能指针,数据通道源和数据通道接收器作为参数。 应用程序被编译以产生在应用程序中指定的线程之间的数据流的描述。 硬件被配置为具有可操作以根据流描述符定义访问存储器的流式存储器接口设备,可操作以根据计算线程定义处理数据的数据路径设备和可操作以连接数据路径设备和流式存储器的数据通道 接口设备按照数据流的描述。

    STREAMING KERNEL SELECTION FOR RECONFIGURABLE PROCESSOR
    5.
    发明申请
    STREAMING KERNEL SELECTION FOR RECONFIGURABLE PROCESSOR 失效
    为可重构加工商流程选择KERNEL选择

    公开(公告)号:US20070213851A1

    公开(公告)日:2007-09-13

    申请号:US11276657

    申请日:2006-03-09

    IPC分类号: G05B13/02

    CPC分类号: G06F8/433

    摘要: In one embodiment, a subset of a set of streaming kernels of an application is selected for implementation on a reconfigurable processor. The streaming kernels are selected by first forming a stream flow graph of the application by parsing a program of instructions of the application, the stream flow graph having kernel nodes and edges, and determining benefit and cost values for each kernel node in the stream flow graph. Next, a subset of the kernel nodes that maximizes a weighted sum of the benefits values is selected, subject to a constraint that the sum of cost values is not greater than a prescribed value for the reconfigurable processor.

    摘要翻译: 在一个实施例中,应用的一组流内核的子集被选择用于在可重新配置的处理器上实现。 通过首先通过解析应用程序的指令程序,具有内核节点和边缘的流流图,并且确定流流图中的每个内核节点的有益和成本值来首先形成应用的流流程图来选择流内核 。 接下来,选择最大化益处值的加权和的内核节点的子集,受到成本值的总和不大于可重构处理器的规定值的约束。

    Method and apparatus for transforming a non-linear lens-distorted image
    6.
    发明授权
    Method and apparatus for transforming a non-linear lens-distorted image 有权
    用于变换非线性透镜失真图像的方法和装置

    公开(公告)号:US08326077B2

    公开(公告)日:2012-12-04

    申请号:US12262363

    申请日:2008-10-31

    IPC分类号: G06K9/40

    摘要: A method and apparatus for image processing a lens-distorted image (e.g., a fisheye image) is provided. The method includes partitioning coordinate points in a selected output image into tiles. The output image is an undistorted rendition of a subset of the lens-distorted image. Coordinate points on a border of the tiles in the output image are selected. For each tile, coordinate points in the lens-distorted image corresponding to each selected coordinate point in the output image are calculated. In addition, for each tile, a bounding box on the lens-distorted image is selected. The bounding box includes the calculated coordinates in the lens-distorted image. The bounding boxes are expanded so that they encompass all coordinate points in the lens-distorted image that map to all coordinate points in their respective corresponding tiles. Output pixel values are generated for each tile from pixel values in their corresponding expanded bounding boxes.

    摘要翻译: 提供了一种用于图像处理镜片失真图像(例如,鱼眼图像)的方法和装置。 该方法包括将所选输出图像中的坐标点分割成瓦片。 输出图像是透镜失真图像的子集的未失真的再现。 选择输出图像中瓦片边框的坐标点。 对于每个瓦片,计算与输出图像中的每个所选坐标点相对应的透镜失真图像中的坐标点。 另外,对于每个瓦片,选择透镜失真图像上的边界框。 边界框包括透镜失真图像中计算的坐标。 边界框被扩展,使得它们包含映射到它们各自对应的瓦片中的所有坐标点的透镜失真图像中的所有坐标点。 从其对应的扩展边界框中的像素值为每个图块生成输出像素值。

    METHOD AND APPARATUS FOR TRANSFORMING A NON-LINEAR LENS-DISTORTED IMAGE
    7.
    发明申请
    METHOD AND APPARATUS FOR TRANSFORMING A NON-LINEAR LENS-DISTORTED IMAGE 有权
    用于变换非线性透镜失真图像的方法和装置

    公开(公告)号:US20100111440A1

    公开(公告)日:2010-05-06

    申请号:US12262363

    申请日:2008-10-31

    IPC分类号: G06K9/54

    摘要: A method and apparatus for image processing a lens-distorted image (e.g., a fisheye image) is provided. The method includes partitioning coordinate points in a selected output image into tiles. The output image is an undistorted rendition of a subset of the lens-distorted image. Coordinate points on a border of the tiles in the output image are selected. For each tile, coordinate points in the lens-distorted image corresponding to each selected coordinate point in the output image are calculated. In addition, for each tile, a bounding box on the lens-distorted image is selected. The bounding box includes the calculated coordinates in the lens-distorted image. The bounding boxes are expanded so that they encompass all coordinate points in the lens-distorted image that map to all coordinate points in their respective corresponding tiles. Output pixel values are generated for each tile from pixel values in their corresponding expanded bounding boxes.

    摘要翻译: 提供了一种用于图像处理镜片失真图像(例如,鱼眼图像)的方法和装置。 该方法包括将所选输出图像中的坐标点分割成瓦片。 输出图像是透镜失真图像的子集的未失真的再现。 选择输出图像中瓦片边框的坐标点。 对于每个瓦片,计算与输出图像中的每个所选坐标点相对应的透镜失真图像中的坐标点。 另外,对于每个瓦片,选择透镜失真图像上的边界框。 边界框包括透镜失真图像中计算的坐标。 边界框被扩展,使得它们包含映射到它们各自对应的瓦片中的所有坐标点的透镜失真图像中的所有坐标点。 从其对应的扩展边界框中的像素值为每个图块生成输出像素值。

    Dynamic access scheduling memory controller
    8.
    发明授权
    Dynamic access scheduling memory controller 失效
    动态访问调度内存控制器

    公开(公告)号:US07363406B2

    公开(公告)日:2008-04-22

    申请号:US11007704

    申请日:2004-12-08

    IPC分类号: G06F13/14

    CPC分类号: G06F13/161 Y02D10/14

    摘要: Bus transactions in a memory controller are scheduled by storing a set of configuration parameters that define a bus scheduling policy, generating values of a set of dynamic cost functions for each bus transaction, ordering the bus transactions in accordance with the bus scheduling policy to produce ordered bus transactions and generating a memory transaction that is derived from the ordered bus transactions. The memory controller includes one or more control registers for storing the set of configuration parameters, a bus interface operable to capture bus transactions from applications, a set of buffers operable to store the bus transactions and the set of dynamic cost functions and one or more registers operable to store the statistical data and a cost policy. The memory controller selects the order of the bus transactions based on an arbitration and selection policy and generates memory transactions to an external memory.

    摘要翻译: 通过存储定义总线调度策略的一组配置参数来调度存储器控制器中的总线事务,为每个总线事务生成一组动态成本函数的值,根据总线调度策略排序总线事务以产生有序 总线事务并生成从有序总线事务导出的内存事务。 所述存储器控制器包括用于存储所述一组配置参数的一个或多个控制寄存器,用于从应用程序捕获总线事务的总线接口,可用于存储所述总线事务和一组动态成本函数的一组缓冲器以及一个或多个寄存器 可操作地存储统计数据和成本政策。 存储器控制器基于仲裁和选择策略选择总线事务的顺序,并且向外部存储器生成存储器事务。