公开(公告)号：US07961018B2

公开(公告)日：2011-06-14

申请号：US12588571

申请日：2009-10-20

申请人： Seok-Hun Hyun ,  Kye-Hyun Kyung ,  Jun-Ho Shin

发明人： Seok-Hun Hyun ,  Kye-Hyun Kyung ,  Jun-Ho Shin

IPC分类号： H03L7/06

CPC分类号： H03L7/0814

摘要： A delay locked loop adapted to delay an external clock signal and to output an internal clock signal, the delay locked loop including a renewal signal generator that outputs a renewal signal that is selectively activated and inactivated, a replica path that is active when the renewal signal is activated and is inactive when the renewal signal is inactivated, the replica path delaying the internal clock signal by a delay time of a normal path of a semiconductor device to output a replica internal clock signal when the renewal signal is activated, a control signal generator adapted to vary and to output a delay control signal according to a phase difference between the external and the replica internal clock signals, and a variable delay circuit adapted to delay the external clock signal by a time corresponding to the delay control signal and to output the internal clock signal.

摘要翻译： 一种延迟锁定环路，适于延迟外部时钟信号并输出​​内部时钟信号，所述延迟锁定环路包括更新信号发生器，所述更新信号发生器输出被选择性地激活和去激活的更新信号，所述更新信号在所述更新信号 被激活，并且当更新信号被去激活时不活动，复制路径延迟内部时钟信号延迟半导体器件的正常路径的延迟时间，以在更新信号被激活时输出复制内部时钟信号;控制信号发生器 适于改变并根据外部和复制内部时钟信号之间的相位差输出延迟控制信号，以及可变延迟电路，其适于将外部时钟信号延迟与延迟控制信号相对应的时间，并输出 内部时钟信号。

公开(公告)号：US20100097111A1

公开(公告)日：2010-04-22

申请号：US12588571

申请日：2009-10-20

申请人： Seok-Hun Hyun ,  Kye-Hyun Kyung ,  Jun-Ho Shin

发明人： Seok-Hun Hyun ,  Kye-Hyun Kyung ,  Jun-Ho Shin

IPC分类号： H03L7/06

CPC分类号： H03L7/0814

摘要： A delay locked loop adapted to delay an external clock signal and to output an internal clock signal, the delay locked loop including a renewal signal generator that outputs a renewal signal that is selectively activated and inactivated, a replica path that is active when the renewal signal is activated and is inactive when the renewal signal is inactivated, the replica path delaying the internal clock signal by a delay time of a normal path of a semiconductor device to output a replica internal clock signal when the renewal signal is activated, a control signal generator adapted to vary and to output a delay control signal according to a phase difference between the external and the replica internal clock signals, and a variable delay circuit adapted to delay the external clock signal by a time corresponding to the delay control signal and to output the internal clock signal.

摘要翻译： 一种延迟锁定环路，适于延迟外部时钟信号并输出​​内部时钟信号，所述延迟锁定环路包括更新信号发生器，所述更新信号发生器输出被选择性地激活和去激活的更新信号，所述更新信号在所述更新信号 被激活，并且当更新信号被去激活时不活动，复制路径延迟内部时钟信号延迟半导体器件的正常路径的延迟时间，以在更新信号被激活时输出复制内部时钟信号;控制信号发生器 适于改变并根据外部和复制内部时钟信号之间的相位差输出延迟控制信号，以及可变延迟电路，其适于将外部时钟信号延迟与延迟控制信号相对应的时间，并输出 内部时钟信号。

公开(公告)号：US20060193196A1

公开(公告)日：2006-08-31

申请号：US11350249

申请日：2006-02-07

申请人： Jun-Ho Shin

发明人： Jun-Ho Shin

IPC分类号： G11C8/00

CPC分类号： G11C7/12 ,  G11C7/1048

摘要： We describe a semiconductor memory device having a precharge control circuit and an associated method for precharging the same. A semiconductor memory device having a series of circuits for writing data to memory cells includes an input and output line for transferring data to be written to each of the memory cells. A precharge control circuit is adapted to generate a precharge control signal for controlling a precharge disable state of the input and output line after application of a first write command. The disable state of the precharge control signal is maintained even after application of a second write command when performing a continuous write operation responsive to the second write command application without other commands applied subsequent to the first write command application. Avoiding precharging the input and output line in a continuous write operation, reduces current consumption.

摘要翻译： 我们描述一种具有预充电控制电路的半导体存储器件以及用于对其进行预充电的相关方法。 具有用于向存储单元写入数据的一系列电路的半导体存储器件包括用于传送要写入每个存储器单元的数据的输入和输出线。 预充电控制电路适于产生用于在施加第一写入命令之后控制输入和输出线的预充电禁止状态的预充电控制信号。 即使在第二写命令应用之后，当执行连续写入操作时，预充电控制信号的禁止状态也被保持，响应于第二写入命令应用，而不在第一写入命令应用之后施加其他命令。 避免在连续写入操作中对输入和输出线进行预充电，从而降低电流消耗。

公开(公告)号：US20060181937A1

公开(公告)日：2006-08-17

申请号：US11172256

申请日：2005-06-30

申请人： Sung-Ho Choi ,  Jun-Ho Shin ,  Seung-Hoon Lee

发明人： Sung-Ho Choi ,  Jun-Ho Shin ,  Seung-Hoon Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C5/147

摘要： An internal supply voltage generation circuit is provided that is within a semiconductor memory device, and that is configured to generate an internal supply voltage to a memory array in the semiconductor memory device. The internal supply voltage generation circuit includes an internal driving unit, an internal transmission unit, and an internal sensing unit. The internal driving unit is configured to generate a driving current and a preliminary voltage responsive to an external supply voltage that is supplied from external to the semiconductor memory device, and it varies a magnitude of the driving current responsive to a driving control signal. The internal transmission unit is configured to generate the internal supply voltage responsive to the preliminary voltage from the internal driving unit, and to vary a level of the internal supply voltage to be at least a defined voltage difference less than a boosted voltage. The boosted voltage is greater than the external supply voltage. The internal sensing unit is configured to generate the driving control signal responsive to the internal supply voltage so that the internal supply voltage is maintained at a constant level.

摘要翻译： 提供内部电源电压生成电路，其在半导体存储器件内，并且被配置为向半导体存储器件中的存储器阵列产生内部电源电压。 内部电源电压产生电路包括内部驱动单元，内部传输单元和内部感测单元。 内部驱动单元被配置为响应于从外部向半导体存储器件提供的外部电源电压产生驱动电流和初始电压，并且响应于驱动控制信号而改变驱动电流的大小。 内部传输单元被配置为响应于来自内部驱动单元的初步电压而产生内部电源电压，并且将内部电源电压的电平改变为至少一个小于升压电压的限定电压差。 升压电压大于外部电源电压。 内部感测单元被配置为响应于内部电源电压产生驱动控制信号，使得内部电源电压保持在恒定水平。

公开(公告)号：US07463538B2

公开(公告)日：2008-12-09

申请号：US11350249

申请日：2006-02-07

申请人： Jun-Ho Shin

发明人： Jun-Ho Shin

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/1048

摘要： We describe a semiconductor memory device having a precharge control circuit and an associated method for precharging the same. A semiconductor memory device having a series of circuits for writing data to memory cells includes an input and output line for transferring data to be written to each of the memory cells. A precharge control circuit is adapted to generate a precharge control signal for controlling a precharge disable state of the input and output line after application of a first write command. The disable state of the precharge control signal is maintained even after application of a second write command when performing a continuous write operation responsive to the second write command application without other commands applied subsequent to the first write command application. Avoiding precharging the input and output line in a continuous write operation, reduces current consumption.

摘要翻译： 我们描述一种具有预充电控制电路的半导体存储器件以及用于对其进行预充电的相关方法。 具有用于向存储单元写入数据的一系列电路的半导体存储器件包括用于传送要写入每个存储器单元的数据的输入和输出线。 预充电控制电路适于产生用于在施加第一写入命令之后控制输入和输出线的预充电禁止状态的预充电控制信号。 即使在第二写命令应用之后，当执行连续写入操作时，预充电控制信号的禁止状态也被保持，响应于第二写入命令应用，而不在第一写入命令应用之后施加其他命令。 避免在连续写入操作中对输入和输出线进行预充电，从而降低电流消耗。

公开(公告)号：US20100013847A1

公开(公告)日：2010-01-21

申请号：US12438857

申请日：2007-09-06

申请人： Jun-Ho Shin

发明人： Jun-Ho Shin

IPC分类号： G09G5/02 ,  G09G5/10

CPC分类号： G09G3/3406 ,  G09G2320/0233 ,  G09G2320/0285 ,  G09G2320/0626 ,  G09G2360/16 ,  H04N5/20

摘要： Provided an apparatus and method for controlling luminance of a display device. The apparatus includes an analog digital converter (ADC), a video processor, a control unit, and a display unit. The ADC converts input image data into a digital signal. The video processor converts the digital signal output from the ADC into a format suitable for a display module. The control unit receives the formatted signal from the video processor and converts a luminance level of the formatted signal into modified luminance levels so as to reduce differences between output luminance levels across pixel regions of the display module. The display unit displays the input image data using the formatted signal according to the modified luminance levels.

摘要翻译： 提供一种用于控制显示装置的亮度的装置和方法。 该装置包括模拟数字转换器（ADC），视频处理器，控制单元和显示单元。 ADC将输入图像数据转换为数字信号。 视频处理器将从ADC输出的数字信号转换为适合显示模块的格式。 控制单元接收来自视频处理器的格式化信号，并将格式化信号的亮度电平转换成修改的亮度级，以便减少显示模块的像素区域之间的输出亮度级之间的差异。 显示单元根据修改的亮度水平使用格式化的信号显示输入图像数据。

公开(公告)号：US07248510B2

公开(公告)日：2007-07-24

申请号：US11172256

申请日：2005-06-30

申请人： Sung-Ho Choi ,  Jun-Ho Shin ,  Seung-Hoon Lee

发明人： Sung-Ho Choi ,  Jun-Ho Shin ,  Seung-Hoon Lee

IPC分类号： G11C5/14 ,  G05F1/10

CPC分类号： G11C7/12 ,  G11C5/147

摘要： An internal supply voltage generation circuit is provided that is within a semiconductor memory device, and that is configured to generate an internal supply voltage to a memory array in the semiconductor memory device. The internal supply voltage generation circuit includes an internal driving unit, an internal transmission unit, and an internal sensing unit. The internal driving unit is configured to generate a driving current and a preliminary voltage responsive to an external supply voltage that is supplied from external to the semiconductor memory device, and it varies a magnitude of the driving current responsive to a driving control signal. The internal transmission unit is configured to generate the internal supply voltage responsive to the preliminary voltage from the internal driving unit, and to vary a level of the internal supply voltage to be at least a defined voltage difference less than a boosted voltage. The boosted voltage is greater than the external supply voltage. The internal sensing unit is configured to generate the driving control signal responsive to the internal supply voltage so that the internal supply voltage is maintained at a constant level.

摘要翻译： 提供内部电源电压生成电路，其在半导体存储器件内，并且被配置为向半导体存储器件中的存储器阵列产生内部电源电压。 内部电源电压产生电路包括内部驱动单元，内部传输单元和内部感测单元。 内部驱动单元被配置为响应于从外部向半导体存储器件提供的外部电源电压产生驱动电流和初始电压，并且响应于驱动控制信号而改变驱动电流的大小。 内部传输单元被配置为响应于来自内部驱动单元的初步电压而产生内部电源电压，并且将内部电源电压的电平改变为至少一个小于升压电压的限定电压差。 升压电压大于外部电源电压。 内部感测单元被配置为响应于内部电源电压产生驱动控制信号，使得内部电源电压保持在恒定水平。