公开(公告)号：US20170207220A1

公开(公告)日：2017-07-20

申请号：US15295034

申请日：2016-10-17

申请人： Seok-Jung YUN ,  Joon-Hee LEE ,  Seong Soon CHO

发明人： Seok-Jung YUN ,  Joon-Hee LEE ,  Seong Soon CHO

IPC分类号： H01L27/105 ,  H01L29/78

CPC分类号： H01L27/11551 ,  H01L27/1052 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11597 ,  H01L28/00 ,  H01L29/7827 ,  H01L29/7889 ,  H01L29/7926

摘要： A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the first direction and having a first width in a third direction perpendicular to the first and second directions, a dummy word line over an uppermost word line, including an opening and having a portion thereof with the first width in the third direction, a first string selection line (SSL) and a second string selection line (SSL) over the dummy word line, the first and second SSLs being at substantially the same level along the first direction, each of the first and second SSLs having a second width less than the first width in the third direction, and a plurality of vertical channel structures, each through the word lines, the dummy word line, and one of the first and second SSLs.

公开(公告)号：US20170179025A1

公开(公告)日：2017-06-22

申请号：US15256226

申请日：2016-09-02

申请人： Seok-Jung YUN ,  Sung-Hun LEE ,  Jee-Hoon HAN ,  Yong-Won CHUNG ,  Seong Soon CHO

发明人： Seok-Jung YUN ,  Sung-Hun LEE ,  Jee-Hoon HAN ,  Yong-Won CHUNG ,  Seong Soon CHO

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/115

摘要： Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a first direction and extend in a second direction. The device may also include a first step pattern structure including extended gate lines extending from the gate lines and including first step layers and a second step pattern structure contacting the first step pattern structure, including the extended gate lines and including second step layers. An n-th extended gate line (n is an even number) may be disposed at an upper portion of each of the first step layers, and an (n−1)-th extended gate line may be disposed at an upper portion of each of the second step layers. Each of exposed portions of the (n−1)-th extended gate lines serves as a pad region, and the pad regions have different areas.