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    Methods of Forming Semiconductor Devices to Include Single Body Interconnection Patterns Using Fine Patterning Techniques, and Semiconductor Device So Formed
    1.
    发明申请
    Methods of Forming Semiconductor Devices to Include Single Body Interconnection Patterns Using Fine Patterning Techniques, and Semiconductor Device So Formed 有权
    使用精细图案化技术形成半导体器件以包括单体互连模式的方法以及如此形成的半导体器件

    公开(公告)号：US20150371685A1

    公开(公告)日：2015-12-24

    申请号：US14682132

    申请日：2015-04-09

    申请人： Seok-ho Shin ,  Chul Lee

    发明人： Seok-ho Shin ,  Chul Lee

    IPC分类号： G11C5/06 ,  H01L23/528 ,  H01L29/06

    CPC分类号： H01L29/0649 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894

    摘要： A method of forming fine patterns for a semiconductor device includes providing a substrate with a first region and a second region, forming a conductive layer on the substrate, the conductive layer including a plate portion covering the first region and first protruding portions extending from the plate portion in a first direction and covering a portion of the second region, forming first mask patterns on the conductive layer, the first mask patterns extending in the first direction and being spaced apart from each other in a second direction crossing the first direction, forming a second mask pattern on the second region to cover the first protruding portions, and patterning the conductive layer using the first and second mask patterns as an etch mask to form conductive patterns. In plan view, each of the first protruding portions is overlapped with a corresponding one of the first mask patterns.

    摘要翻译： 一种形成半导体器件的精细图案的方法包括：提供具有第一区域和第二区域的衬底，在衬底上形成导电层，所述导电层包括覆盖第一区域的板部分和从板延伸的第一突出部分 部分在第一方向上并且覆盖第二区域的一部分，在导电层上形成第一掩模图案，第一掩模图案沿第一方向延伸并且在与第一方向交叉的第二方向上彼此间隔开，形成 在第二区域上的第二掩模图案，以覆盖第一突出部分，并且使用第一和第二掩模图案将导电层图案化为蚀刻掩模以形成导电图案。 在平面图中，每个第一突出部分与第一掩模图案中的相应一个重叠。

    Methods of forming semiconductor devices to include single body interconnection patterns using fine patterning techniques, and semiconductor device so formed
    2.
    发明授权
    Methods of forming semiconductor devices to include single body interconnection patterns using fine patterning techniques, and semiconductor device so formed 有权
    使用精细图案形成技术形成半导体器件以包括单体互连图案的方法，以及如此形成的半导体器件

    公开(公告)号：US09590034B2

    公开(公告)日：2017-03-07

    申请号：US14682132

    申请日：2015-04-09

    申请人： Seok-ho Shin ,  Chul Lee

    发明人： Seok-ho Shin ,  Chul Lee

    IPC分类号： H01L29/06 ,  H01L27/02 ,  H01L27/108 ,  H01L21/768

    CPC分类号： H01L29/0649 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894

    摘要： A method of forming fine patterns for a semiconductor device includes providing a substrate with a first region and a second region, forming a conductive layer on the substrate, the conductive layer including a plate portion covering the first region and first protruding portions extending from the plate portion in a first direction and covering a portion of the second region, forming first mask patterns on the conductive layer, the first mask patterns extending in the first direction and being spaced apart from each other in a second direction crossing the first direction, forming a second mask pattern on the second region to cover the first protruding portions, and patterning the conductive layer using the first and second mask patterns as an etch mask to form conductive patterns. In plan view, each of the first protruding portions is overlapped with a corresponding one of the first mask patterns.

    摘要翻译： 一种形成半导体器件的精细图案的方法包括：提供具有第一区域和第二区域的衬底，在衬底上形成导电层，所述导电层包括覆盖第一区域的板部分和从板延伸的第一突出部分 部分在第一方向上并且覆盖第二区域的一部分，在导电层上形成第一掩模图案，第一掩模图案沿第一方向延伸并且在与第一方向交叉的第二方向上彼此间隔开，形成 在第二区域上的第二掩模图案，以覆盖第一突出部分，并且使用第一和第二掩模图案将导电层图案化为蚀刻掩模以形成导电图案。 在平面图中，每个第一突出部分与第一掩模图案中的相应一个重叠。

    HEALTH TRACKING SYSTEM WITH VERIFICATION OF NUTRITION INFORMATION
    3.
    发明公开
    HEALTH TRACKING SYSTEM WITH VERIFICATION OF NUTRITION INFORMATION 审中-公开

    公开(公告)号：US20230230671A1

    公开(公告)日：2023-07-20

    申请号：US17992424

    申请日：2022-11-22

    申请人： Chul Lee ,  Hesamoddin Salehian

    发明人： Chul Lee ,  Hesamoddin Salehian

    IPC分类号： G16H20/60 ,  G06F7/36 ,  G16H50/30 ,  G16H10/60

    CPC分类号： G16H20/60 ,  G06F7/36 ,  G16H50/30 ,  G16H10/60

    摘要： A method for decreasing a number of individual entries in a database of user-created records which describe a single item by: receiving a plurality of user-created records, each of said records comprising at least a descriptive string; placing individual ones of the plurality of user-created records having a sufficiently similar descriptive string into one of a plurality of first groups; hashing the descriptive string of each of the plurality of first groups in order to place two or more groups into a single bin; performing a pair-wise comparison of the descriptive strings of the two or more groups in each bin; and when the comparison of the descriptive strings of the two or more groups in a bin results in a distance below a first threshold, merging the two or more groups into a combined group.

    Recessed transistor and method of manufacturing the same
    4.
    发明授权
    Recessed transistor and method of manufacturing the same 有权
    嵌入式晶体管及其制造方法

    公开(公告)号：US09012982B2

    公开(公告)日：2015-04-21

    申请号：US12068179

    申请日：2008-02-04

    申请人： Keun-Nam Kim ,  Makoto Yoshida ,  Chul Lee ,  Dong-Gun Park ,  Woun-Suck Yang

    发明人： Keun-Nam Kim ,  Makoto Yoshida ,  Chul Lee ,  Dong-Gun Park ,  Woun-Suck Yang

    IPC分类号： H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/66795 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7851

    摘要： A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.

    摘要翻译： 提供凹陷晶体管及其制造方法。 凹陷的晶体管可以包括衬底，有源引脚，栅极图案以及源极和漏极区域。 衬底可以包括建立衬底的有源区和场区的隔离层。 衬底可以包括具有形成在有源区域中的上凹部的凹陷结构和与上凹部连通的下凹部。 有源销可以形成在隔离层和下凹部的侧表面之间的区域中以及有源区域和场区域之间的界面。 栅极图案可以包括形成在凹陷结构的内表面上的栅极绝缘层和形成在凹陷结构中的栅极绝缘层上的栅电极。 源/漏区可以与有源区和栅电极相邻形成。

    Semiconductor Devices Including Transistors Having Three Dimensional Channels
    9.
    发明申请
    Semiconductor Devices Including Transistors Having Three Dimensional Channels 审中-公开
    包括具有三维通道的晶体管的半导体器件

    公开(公告)号：US20080315282A1

    公开(公告)日：2008-12-25

    申请号：US12199237

    申请日：2008-08-27

    申请人： Eun-Suk Cho ,  Chul Lee

    发明人： Eun-Suk Cho ,  Chul Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L23/485 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor devices including a gate electrode crossing over a semiconductor fin on a semiconductor substrate are provided. A gate insulating layer is provided between the gate electrode and the semiconductor fin. A channel region having a three-dimensional structure defined at the semiconductor fin under the gate electrode is also provided. Doped region is provided in the semiconductor fin at either side of the gate electrode and an interlayer insulating layer is provided on a surface of the semiconductor substrate. A connector region is coupled to the doped region and provided in an opening, which penetrates the interlayer insulating layer. A recess region is provided in the doped region and is coupled to the connector region. The connector region contacts an inner surface of the recess region. Related methods of fabricating semiconductor devices are also provided herein.

    摘要翻译： 提供包括在半导体衬底上与半导体鳍状物交叉的栅电极的半导体器件。 栅极绝缘层设置在栅电极和半导体鳍之间。 还提供了在栅电极下方的半导体鳍片处限定的具有三维结构的沟道区域。 掺杂区域设置在栅电极的任一侧的半导体鳍片中，并且在半导体衬底的表面上设置层间绝缘层。 连接器区域耦合到掺杂区域并且设置在穿过层间绝缘层的开口中。 在掺杂区域中提供凹陷区域并且耦合到连接器区域。 连接器区域接触凹部区域的内表面。 本文还提供了制造半导体器件的相关方法。

    Fin field effect transistor device and method of fabricating the same
    10.
    发明授权
    Fin field effect transistor device and method of fabricating the same 失效
    Fin场效应晶体管器件及其制造方法

    公开(公告)号：US07323375B2

    公开(公告)日：2008-01-29

    申请号：US11091457

    申请日：2005-03-28

    申请人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

    发明人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

    IPC分类号： H01L21/00

    CPC分类号： H01L29/7851 ,  H01L21/84 ,  H01L29/66795

    摘要： Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer is selectively etched-back to define sacrificial spacers on sidewalls of the fin-shaped semiconductor active region. The electrically insulating region is formed on the sacrificial spacers. The sacrificial spacers are then removed by selectively etching the sacrificial spacers using the electrically insulating region as an etching mask. An insulated gate electrode is then formed on the sidewalls of the fin-shaped semiconductor active region.

    摘要翻译： 形成具有鳍状有源区的场效应晶体管（FET）的方法包括图案化半导体衬底以在其中限定由沟槽包围的鳍状半导体有源区。 鳍形半导体有源区域的至少上部被牺牲层覆盖。 该牺牲层被有选择地回蚀刻以在鳍状半导体有源区域的侧壁上限定牺牲隔离物。 电绝缘区域形成在牺牲间隔物上。 然后通过使用电绝缘区域作为蚀刻掩模选择性地蚀刻牺牲隔离物来去除牺牲间隔物。 然后在鳍状半导体有源区的侧壁上形成绝缘栅电极。