-
1.发明授权Signal amplitude detection circuitry without pattern dependencies for high-speed serial links 有权信号幅度检测电路，无高速串行链路的模式相关性公开(公告)号：US07576570B1
公开(公告)日：2009-08-18
申请号：US11508607
申请日：2006-08-22
IPC分类号： H03K5/153
摘要： Precision amplitude detection circuitry without pattern dependencies is provided that includes rectifier circuitry to output a rectified voltage signal and delay circuitry to send one or more delayed or phase-shifted versions of a differential signal input to the rectifier circuitry. The delayed versions of the differential signal input may be delayed in order to reduce or eliminate the dips in the input seen by the rectifier. This may help correct for low rectified voltage levels. The signal amplitude detection circuitry of the present invention may be incorporated on the input pin of any programmable logic resource and may be included in communication circuitry of a PLD. The precision amplitude detection circuitry may operate in the Gbps (gigabit per second) range.
摘要翻译： 提供了没有图形相关性的精密幅度检测电路，其包括整流电路，用于输出整流电压信号和延迟电路，以将一个或多个差分信号输入的延迟或相移版本发送到整流器电路。 可以延迟差分信号输入的延迟版本，以便减少或消除由整流器看到的输入中的下降。 这可能有助于校正低整流电压电平。 本发明的信号幅度检测电路可以结合在任何可编程逻辑资源的输入引脚上，并且可以被包括在PLD的通信电路中。 精度幅度检测电路可以以Gbps（千兆位/秒）范围工作。
-
2.发明授权Increased sensitivity and reduced offset variation in high data rate HSSI receiver 有权在高数据速率HSSI接收机中增加灵敏度和减少偏移变化公开(公告)号：US07777526B2
公开(公告)日：2010-08-17
申请号：US12134777
申请日：2008-06-06
IPC分类号： H03K19/094
CPC分类号： H03K19/018514 , H03F3/45197 , H03F2203/45494 , H03F2203/45686
摘要： Signal offset variation caused by transistor variation/mismatch in integrated circuits may be reduced. In one embodiment, a buffer circuit has variable-valued circuit elements. Offset variation measurements are made and the variable-valued circuit elements are calibrated to reduce the measured offset variation. In another embodiment, each amplifying stage of a multi-stage buffer provides variable gain. The total DC gain of the cascade is distributed unevenly across the stages, with more DC gain being provided by amplifier stages at the beginning of the cascade than at the end. An additional pre-amplifier stage can also be provided at the beginning of the cascade.
摘要翻译： 集成电路中晶体管变化/失配引起的信号偏移变化可能会降低。 在一个实施例中，缓冲电路具有可变值电路元件。 进行偏移变化测量，并校准可变值电路元件以减少测量的偏移变化。 在另一个实施例中，多级缓冲器的每个放大级提供可变增益。 级联的总直流增益不均匀地分布在整个级中，在级联开始时比放大器级提供更多的直流增益。 在级联开始时也可以提供一个额外的前级放大器级。
-
3.发明授权公开(公告)号：US07920621B2
公开(公告)日：2011-04-05
申请号：US11522284
申请日：2006-09-14
申请人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H03H7/30
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译： 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。
-
4.发明授权High-speed serial interface circuitry for programmable logic device integrated circuits 有权用于可编程逻辑器件集成电路的高速串行接口电路公开(公告)号：US07688106B1
公开(公告)日：2010-03-30
申请号：US11712609
申请日：2007-02-27
IPC分类号： H03K19/173
CPC分类号： H03K19/17744
摘要： High-speed serial interface (“HSSI”) transceiver circuitry (e.g., on a programmable logic device (“PLD”) integrated circuit) includes input buffer circuitry with adaptive equalization capability. The transceiver circuitry also includes an output driver, which may include pre-emphasis capability (preferably controllably settable). Selectively usable loop-back circuitry is provided for allowing the output signal of the input buffer to be applied substantially directly to the output driver. The loop-back circuitry may include a loop-back driver, which may be turned on substantially only when needed for loop-back operations.
摘要翻译： 高速串行接口（“HSSI”）收发器电路（例如，在可编程逻辑器件（“PLD”）集成电路上）包括具有自适应均衡能力的输入缓冲器电路。 收发器电路还包括输出驱动器，其可以包括预加重功能（优选可控地设置）。 提供了可选择的环回电路，用于使输入缓冲器的输出信号基本上直接施加到输出驱动器。 环回电路可以包括环回驱动器，其可以基本上仅在环回操作需要时被导通。
-
5.发明授权公开(公告)号：US08208523B2
公开(公告)日：2012-06-26
申请号：US13079420
申请日：2011-04-04
申请人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H03H7/30
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译： 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。
-
6.发明申请公开(公告)号：US20110188564A1
公开(公告)日：2011-08-04
申请号：US13079420
申请日：2011-04-04
申请人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Sergey Shumarayev , Simardeep Maangat , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译： 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。
-
公开(公告)号：US07586983B1
公开(公告)日：2009-09-08
申请号：US11510446
申请日：2006-08-24
CPC分类号： H04L25/03057
摘要： In high speed receiver circuitry (e.g., on a programmable logic device (PLD) or the like), decision feedback equalization (DFE) circuitry is used to at least partly cancel unwanted offset (e.g., from other elements of the receiver). The data input to the receiver is tristated; and then each DFE tap coefficient is varied in turn to find coefficient values that are associated with transitions between oscillation and non-oscillation of the receiver output signal. The coefficient values found in this way are used to select trial values. If the output signal of the receiver does not oscillate when these trial values are used, the process is repeated starting from these (or subsequent) trial values until a final set of trial values does allow oscillation of the receiver output signal.
摘要翻译： 在高速接收机电路（例如，在可编程逻辑器件（PLD）等上）中，使用判决反馈均衡（DFE）电路来至少部分地消除不期望的偏移（例如，从接收机的其他元件）。 输入到接收机的数据被三态化; 然后依次改变每个DFE抽头系数，以找到与接收机输出信号的振荡和非振荡之间的转换相关联的系数值。 以这种方式找到的系数值用于选择试验值。 如果接收机的输出信号在使用这些试验值时不振荡，则从这些（或后续）试验值开始重复该过程，直到最终的试验值确定允许接收器输出信号的振荡。
-
8.发明授权High-speed serial interface circuitry for programmable logic device integrated circuits 有权用于可编程逻辑器件集成电路的高速串行接口电路公开(公告)号：US07944235B1
公开(公告)日：2011-05-17
申请号：US12709360
申请日：2010-02-19
IPC分类号： H03K19/173
CPC分类号： H03K19/17744
摘要： High-speed serial interface (“HSSI”) transceiver circuitry (e.g., on a programmable logic device (“PLD”) integrated circuit) includes input buffer circuitry with adaptive equalization capability. The transceiver circuitry also includes an output driver, which may include pre-emphasis capability (preferably controllably settable). Selectively usable loop-back circuitry is provided for allowing the output signal of the input buffer to be applied substantially directly to the output driver. The loop-back circuitry may include a loop-back driver, which may be turned on substantially only when needed for loop-back operations.
摘要翻译： 高速串行接口（“HSSI”）收发器电路（例如，在可编程逻辑器件（“PLD”）集成电路上）包括具有自适应均衡能力的输入缓冲器电路。 收发器电路还包括输出驱动器，其可以包括预加重功能（优选可控地设置）。 提供了可选择的环回电路，用于使输入缓冲器的输出信号基本上直接施加到输出驱动器。 环回电路可以包括环回驱动器，其可以基本上仅在环回操作需要时被导通。
-
9.发明申请INCREASED SENSITIVITY AND REDUCED OFFSET VARIATION IN HIGH DATA RATE HSSI RECEIVER 有权在高数据速率HSSI接收器中提高灵敏度和降低偏移公开(公告)号：US20090302888A1
公开(公告)日：2009-12-10
申请号：US12134777
申请日：2008-06-06
IPC分类号： H03K19/0175
CPC分类号： H03K19/018514 , H03F3/45197 , H03F2203/45494 , H03F2203/45686
摘要： Signal offset variation caused by transistor variation/mismatch in integrated circuits may be reduced. In one embodiment, a buffer circuit has variable-valued circuits elements. Offset variation measurements are made and the variable-valued circuit elements are calibrated to reduce the measured offset variation. In another embodiment, each amplifying stage of a multi-stage buffer provides variable gain. The total DC gain of the cascade is distributed unevenly across the stages, with more DC gain being provided by amplifier stages at the beginning of the cascade than at the end. An additional pre-amplifier stage can also be provided at the beginning of the cascade.
摘要翻译： 集成电路中晶体管变化/失配引起的信号偏移变化可能会降低。 在一个实施例中，缓冲电路具有可变值电路元件。 进行偏移变化测量，并校准可变值电路元件以减少测量的偏移变化。 在另一个实施例中，多级缓冲器的每个放大级提供可变增益。 级联的总直流增益不均匀地分布在整个级中，在级联开始时比放大器级提供更多的直流增益。 在级联开始时也可以提供一个额外的前级放大器级。
-
10.发明申请公开(公告)号：US20080069276A1
公开(公告)日：2008-03-20
申请号：US11522284
申请日：2006-09-14
申请人： Wilson Wong , Doris Po Ching Chan , Simardeep Maangat , Sergey Shumarayev , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Simardeep Maangat , Sergey Shumarayev , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H04B1/10
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译： 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。
-
-
-
-
-
-
-
-
-
搜索结果
35 条记录 (耗时 0.018 秒)