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    MEMORY SYSTEM AND METHOD
    1.
    发明申请
    MEMORY SYSTEM AND METHOD 审中-公开
    记忆系统和方法

    公开(公告)号：US20140019833A1

    公开(公告)日：2014-01-16

    申请号：US14031620

    申请日：2013-09-19

    申请人： Seung-Jun Bae ,  Kwang-II Park ,  Young-Soo Sohn ,  Young-Hyun Jun ,  Joo-Sun Choi ,  Tae-Young Oh

    发明人： Seung-Jun Bae ,  Kwang-II Park ,  Young-Soo Sohn ,  Young-Hyun Jun ,  Joo-Sun Choi ,  Tae-Young Oh

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1004 ,  H03M13/09

    摘要： A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.

    摘要翻译： 存储器系统包括存储器控制器和存储器件。 存储器件通过第一通道与存储器控制器交换数据，通过与存储器控制器的第二通道交换与数据相关联的第一循环冗余校验（CRC）代码，并且接收包括相关联的第二CRC码的命令/地址分组 具有来自存储器控制器的命令/地址通过第三通道。

    Integrated Circuit Memory Devices Having Internal Command Generators Therein that Support Extended Command Sets Using Independent and Dependent Commands
    3.
    发明申请
    Integrated Circuit Memory Devices Having Internal Command Generators Therein that Support Extended Command Sets Using Independent and Dependent Commands 有权
    具有内部命令生成器的集成电路存储器件，其中支持使用独立和相关命令的扩展命令集

    公开(公告)号：US20090097339A1

    公开(公告)日：2009-04-16

    申请号：US12236978

    申请日：2008-09-24

    申请人： Young-soo Sohn ,  Kwang-II Park ,  Seung-Jun Bae

    发明人： Young-soo Sohn ,  Kwang-II Park ,  Seung-Jun Bae

    IPC分类号： G11C7/00 ,  G11C8/18

    CPC分类号： G11C11/4076 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18

    摘要： Integrated circuit memory devices include an internal command generator and a memory control circuit responsive to an internal command generated by the internal command generator. The internal command generator is configured to generate an internal command in response to a combination of an independent command and at least one dependent command received in sequence by the memory device. For example, the internal command generator may be configured to require the independent command to follow the at least one dependent command in the sequence when generating the internal command from the combination of the independent and dependent commands. Alternatively, the internal command generator may be configured to require the independent command to precede the at least one dependent command in the sequence before generating the internal command from the combination of the independent and dependent commands. These independent and dependent commands may be received by the memory device as respective multi-bit external command signals.

    摘要翻译： 集成电路存储器件包括响应于由内部命令发生器产生的内部命令的内部命令发生器和存储器控制电路。 内部命令生成器被配置为响应于独立命令和由存储器装置依次接收的至少一个依赖命令的组合来生成内部命令。 例如，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令时，要求独立命令遵循序列中的至少一个从属命令。 或者，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令之前，要求独立命令在序列中的至少一个从属命令之前。 这些独立和依赖的命令可以被存储器装置接收为相应的多位外部命令信号。

    Dividing circuit and phase locked loop using the same
    4.
    发明授权
    Dividing circuit and phase locked loop using the same 失效
    分频电路和锁相环使用相同

    公开(公告)号：US07843239B2

    公开(公告)日：2010-11-30

    申请号：US12318385

    申请日：2008-12-29

    申请人： Young-Soo Sohn ,  Kwang-II Park

    发明人： Young-Soo Sohn ,  Kwang-II Park

    IPC分类号： H03L7/06

    CPC分类号： G06G7/16 ,  H03K21/023 ,  H03L7/0891 ,  H03L7/183

    摘要： The PLL includes a selection signal generator configured to output a selection signal varying in response to a first clock signal, and a first dividing circuit configured to divide an externally input reference clock signal by a division ratio and output a first division signal. The first dividing circuit selects one of a plurality of edges of the reference clock signal applied for at least one cycle of the first division signal in response to the selection signal, and synchronizes and generates the first division signal on the basis of the selected edge of the reference clock signal. A second dividing circuit is configured to receive an output clock signal, divide the output clock signal by a division ratio, and output a second division signal. The second dividing circuit selects one of the edges of the reference clock signal applied for at least one cycle of the second division signal in response to the selection signal, and synchronizes and generates the second division signal on the basis of the selected edge of the reference clock signal. A synchronous signal output portion is configured to detect a phase difference between the first and second division signals, generate a control voltage corresponding to the phase difference, and output the output clock signal having a frequency corresponding to the control voltage.

    摘要翻译： PLL包括选择信号发生器，其被配置为输出响应于第一时钟信号而变化的选择信号;以及第一分频电路，被配置为将外部输入的参考时钟信号除以除法比，并输出第一除法信号。 第一分频电路响应于选择信号选择施加到第一分频信号的至少一个周期的参考时钟信号的多个边沿中的一个，并且基于所选择的边沿的同步并产生第一分频信号 参考时钟信号。 第二分频电路被配置为接收输出时钟信号，将输出时钟信号除以分频比，并输出第二除法信号。 第二分频电路响应于选择信号选择施加到第二分频信号的至少一个周期的参考时钟信号的边沿中的一个，并且基于参考的所选择的边沿同步并产生第二除法信号 时钟信号。 同步信号输出部被配置为检测第一和第二除法信号之间的相位差，产生与相位差对应的控制电压，并输出具有与控制电压对应的频率的输出时钟信号。

    HIGH-SPEED PHASE-ADJUSTED QUADRATURE DATA RATE (QDR) TRANSCEIVER AND METHOD THEREOF
    5.
    发明申请
    HIGH-SPEED PHASE-ADJUSTED QUADRATURE DATA RATE (QDR) TRANSCEIVER AND METHOD THEREOF 有权
    高速相位调整数据速率（QDR）收发器及其方法

    公开(公告)号：US20070206428A1

    公开(公告)日：2007-09-06

    申请号：US11612800

    申请日：2006-12-19

    申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Sang-Woong Shin ,  Ho-Young Song

    发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Sang-Woong Shin ,  Ho-Young Song

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

    摘要： A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver. In addition, since source synchronization is realized using a strobe signal, phase noise can be efficiently removed.

    摘要翻译： 提供了一种高速双倍或正交数据速率接口半导体器件及其方法。 用于高速数据传输的发射机（例如，数据传输半导体器件）发送第一选通信号和第二选通信号，第一选通信号和第二选通信号之间具有90度的相位差，第一组（字节）数据和 第二组（字节）数据。 发射机基于从接收机反馈的相位误差信息来调节第一和第二选通信号中的至少一个的相位，然后将相位调整的选通信号发送到接收机。 接收机从发送器接收第一和第二选通信号，并使用第一和第二选通信号接收数据的第一组（字节）和第二组（字节）数据。 接收机不需要锁相环（PLL）或延迟锁定环（DLL），从而减少接收机的电路面积和功耗。 此外，由于使用选通信号实现源同步，因此可以有效地去除相位噪声。

    Semiconductor devices, a system including semiconductor devices and methods thereof
    6.
    发明授权
    Semiconductor devices, a system including semiconductor devices and methods thereof 有权

    公开(公告)号：US07541947B2

    公开(公告)日：2009-06-02

    申请号：US11802886

    申请日：2007-05-25

    申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Woo-Jin Lee

    发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Woo-Jin Lee

    IPC分类号： H03M7/00

    CPC分类号： H03K19/00346 ,  H04L25/03866 ,  H04L25/14 ,  H04L25/4908

    摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

    Semiconductor devices, a system including semiconductor devices and methods thereof
    7.
    发明申请
    Semiconductor devices, a system including semiconductor devices and methods thereof 有权
    半导体器件，包括半导体器件的系统及其方法

    公开(公告)号：US20070290902A1

    公开(公告)日：2007-12-20

    申请号：US11802886

    申请日：2007-05-25

    申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Woo-Jin Lee

    发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Woo-Jin Lee

    IPC分类号： H03M9/00

    CPC分类号： H03K19/00346 ,  H04L25/03866 ,  H04L25/14 ,  H04L25/4908

    摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

    摘要翻译： 提供半导体器件，包括所述半导体器件的系统及其方法。 半导体器件的示例可以接收被调度用于发送的数据，对接收到的数据内的比特数进行加扰，按照给定的伪随机序列排列的加扰顺序。 所接收的数据可以是平衡的，使得等于第一逻辑电平的接收数据内的第一比特数与等于第二逻辑电平的接收数据中的第二比特数之间的差异低于阈值。 然后可以发送平衡和加扰的接收数据。 示例半导体器件可以以任何顺序执行加扰和平衡操作。 类似地，在接收端，另一个半导体器件可以通过对发送的数据进行解扰和不平衡来解码原始数据。 可以基于发送的数据被加扰和平衡的顺序以顺序执行解扰和不平衡操作。

    Reference voltage generators for reducing and/or eliminating termination mismatch
    8.
    发明申请
    Reference voltage generators for reducing and/or eliminating termination mismatch 有权
    用于减少和/或消除终止失配的参考电压发生器

    公开(公告)号：US20070285121A1

    公开(公告)日：2007-12-13

    申请号：US11790014

    申请日：2007-04-23

    申请人： Kwang-II Park ,  Seung-Jun Bae ,  Seong-Jin Jang

    发明人： Kwang-II Park ,  Seung-Jun Bae ,  Seong-Jin Jang

    IPC分类号： H03K19/003

    CPC分类号： H03K19/017545

    摘要： A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator.

    摘要翻译： 一种包括多个传输线的系统，向多个传输线中的每一个输出相应信号的发射机，经由各个传输线接收多个信号中的每一个的接收机，所述接收机包括连接到终端电压的连接路径， 多个终端电路沿着连接路径分布，每个终端电路从连接路径接收唯一的终端电压，接收相应的信号并输出​​终止的输入信号;参考电压发生器，包括连接到公共电压的多个参考电压发生器单元， 每个参考电压发生器单元独特地接收至少一个唯一的终端电压并输出参考电压，以及多个数据输入缓冲器，其接收相应的信号和从参考电压发生器输出的多个参考电压的适当参考电压。

    Majority voter circuits and semiconductor device including the same
    9.
    发明申请
    Majority voter circuits and semiconductor device including the same 审中-公开
    多数选民电路和半导体器件包括相同

    公开(公告)号：US20100148819A1

    公开(公告)日：2010-06-17

    申请号：US12656590

    申请日：2010-02-04

    申请人： Seung-Jun Bae ,  Jeong-Don Lim ,  Gil-Shin Moon ,  Kwang-II Park

    发明人： Seung-Jun Bae ,  Jeong-Don Lim ,  Gil-Shin Moon ,  Kwang-II Park

    IPC分类号： H03K19/23 ,  H03K19/20

    CPC分类号： H03K19/23

    摘要： A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.

    摘要翻译： 多数选民电路被配置为基于第一输入数据和反相的第一输入数据生成选择信号。 第一输入数据和反相的第一输入数据都包括奇数位，奇数位包括第一类型的位和第二类型的位。 所生成的选择信号表示第一输入数据中的第一类型和第二类型的比特大多数。