公开(公告)号：US20080130811A1

公开(公告)日：2008-06-05

申请号：US12029518

申请日：2008-02-12

申请人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-jin Jang

发明人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-jin Jang

IPC分类号： H04L7/00 ,  G11B20/20

CPC分类号： G11C7/22 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222

摘要： A data transmission/reception system can lessen a skew between data and clock signal by substantially reducing a data reception error. The data transmission/reception system using a first clock signal and a second clock signal having a phase difference corresponding to a half of data bit period as compared with the first clock signal includes a skew information extracting unit and a timing control unit. The skew information extracting unit obtains and outputs skew edge information data necessary for a skew removal by sampling data transmitted in a training operating mode as one of the first and second clock signals in a receiving side. The timing control unit receives the skew edge information data through a transmitting side, and compares its phase with a phase of the transmitted data and controls a timing between transmission data and a transmission sampling clock signal applied to a transmission output unit according to the phase comparison result. Time taken in a training operation can be relatively shortened, and circuits of the receiving side can be simplified and power consumption can be relatively reduced.

摘要翻译： 数据发送/接收系统可以通过大幅减少数据接收错误来减少数据和时钟信号之间的偏差。 使用第一时钟信号的数据发送/接收系统和与第一时钟信号相比具有对应于数据位周期的一半的相位差的第二时钟信号包括偏斜信息提取单元和定时控制单元。 偏斜信息提取单元通过在接收侧中作为第一和第二时钟信号之一的训练操作模式中发送的数据采样数据获得并输出偏斜去除所需的倾斜边缘信息数据。 定时控制单元通过发送端接收偏斜边信息数据，并将其相位与发送数据的相位进行比较，并根据相位比较控制发送数据与施加到发送输出单元的发送采样时钟信号之间的定时 结果。 可以相对缩短训练中所花费的时间，并且可以简化接收侧的电路，并且能够相对减少功耗。

公开(公告)号：US08045663B2

公开(公告)日：2011-10-25

申请号：US12029518

申请日：2008-02-12

申请人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-jin Jang

发明人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-jin Jang

IPC分类号： H04L7/00

CPC分类号： G11C7/22 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222

摘要： A data transmission/reception system can lessen a skew between data and clock signal by substantially reducing a data reception error. The data transmission/reception system using a first clock signal and a second clock signal having a phase difference corresponding to a half of data bit period as compared with the first clock signal includes a skew information extracting unit and a timing control unit. The skew information extracting unit obtains and outputs skew edge information data necessary for a skew removal by sampling data transmitted in a training operating mode as one of the first and second clock signals in a receiving side. The timing control unit receives the skew edge information data through a transmitting side, and compares its phase with a phase of the transmitted data and controls a timing between transmission data and a transmission sampling clock signal applied to a transmission output unit according to the phase comparison result. Time taken in a training operation can be relatively shortened, and circuits of the receiving side can be simplified and power consumption can be relatively reduced.

摘要翻译： 数据发送/接收系统可以通过大幅减少数据接收错误来减少数据和时钟信号之间的偏差。 使用第一时钟信号的数据发送/接收系统和与第一时钟信号相比具有对应于数据位周期的一半的相位差的第二时钟信号包括偏斜信息提取单元和定时控制单元。 偏斜信息提取单元通过在接收侧中作为第一和第二时钟信号之一的训练操作模式中发送的数据采样数据获得并输出偏斜去除所需的倾斜边缘信息数据。 定时控制单元通过发送侧接收偏斜边信息数据，并将其相位与发送数据的相位进行比较，并根据相位比较控制发送数据与发送输出单元的发送采样时钟信号之间的定时 结果。 可以相对缩短训练中所花费的时间，并且可以简化接收侧的电路，并且能够相对减少功耗。

公开(公告)号：US20060092717A1

公开(公告)日：2006-05-04

申请号：US11194180

申请日：2005-08-01

申请人： Ho-young Song ,  Seong-jin Jang ,  Kwang-il Park

发明人： Ho-young Song ,  Seong-jin Jang ,  Kwang-il Park

IPC分类号： G11C7/10

CPC分类号： G11C29/023 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012

摘要： A method of determining timing skew between data outputs of a memory device can include writing a predetermined data pattern to a memory device at a first operational frequency that is less than a normal operational frequency used to write non-predetermined data to the memory device. The memory device is read to output the predetermined data pattern therefrom at a second operational frequency that is greater than the first operational frequency and about equal to a normal operational frequency used to read non-predetermined data from the memory device. Timing skew is determined between outputs from the memory device based on the actual time when the predetermined data is provided from the memory device.

摘要翻译： 确定存储器件的数据输出之间的定时偏移的方法可以包括以小于用于将非预定数据写入存储器件的正常工作频率的第一工作频率将预定数据模式写入存储器件。 读取存储器件，以大于第一工作频率的第二工作频率输出预定数据模式，并且大约等于用于从存储器件读取非预定数据的正常工作频率。 基于从存储器件提供预定数据的实际时间，在存储器件的输出之间确定定时偏移。

公开(公告)号：US07558979B2

公开(公告)日：2009-07-07

申请号：US11194180

申请日：2005-08-01

申请人： Ho-young Song ,  Seong-jin Jang ,  Kwang-il Park

发明人： Ho-young Song ,  Seong-jin Jang ,  Kwang-il Park

IPC分类号： G06F1/00 ,  G06F11/00

CPC分类号： G11C29/023 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012

摘要： A method of determining timing skew between data outputs of a memory device can include writing a predetermined data pattern to a memory device at a first operational frequency that is less than a normal operational frequency used to write non-predetermined data to the memory device. The memory device is read to output the predetermined data pattern therefrom at a second operational frequency that is greater than the first operational frequency and about equal to a normal operational frequency used to read non-predetermined data from the memory device. Timing skew is determined between outputs from the memory device based on the actual time when the predetermined data is provided from the memory device.

摘要翻译： 确定存储器件的数据输出之间的定时偏移的方法可以包括以小于用于将非预定数据写入存储器件的正常工作频率的第一工作频率将预定数据模式写入存储器件。 读取存储器件，以大于第一工作频率的第二工作频率输出预定数据模式，并且大约等于用于从存储器件读取非预定数据的正常工作频率。 基于从存储器件提供预定数据的实际时间，在存储器件的输出之间确定定时偏移。

公开(公告)号：US20090271652A1

公开(公告)日：2009-10-29

申请号：US12482265

申请日：2009-06-10

申请人： Ho-young Song ,  Seong-jin Jang ,  Kwang-il Park

发明人： Ho-young Song ,  Seong-jin Jang ,  Kwang-il Park

IPC分类号： G06F1/04 ,  G06F1/08

CPC分类号： G11C29/023 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012

摘要： A method of determining timing skew between data outputs of a memory device can include writing a predetermined data pattern to a memory device at a first operational frequency that is less than a normal operational frequency used to write non-predetermined data to the memory device. The memory device is read to output the predetermined data pattern therefrom at a second operational frequency that is greater than the first operational frequency and about equal to a normal operational frequency used to read non-predetermined data from the memory device. Timing skew is determined between outputs from the memory device based on the actual time when the predetermined data is provided from the memory device.

摘要翻译： 确定存储器件的数据输出之间的定时偏移的方法可以包括以小于用于将非预定数据写入存储器件的正常工作频率的第一工作频率将预定数据模式写入存储器件。 读取存储器件，以大于第一工作频率的第二工作频率输出预定数据模式，并且大约等于用于从存储器件读取非预定数据的正常工作频率。 基于从存储器件提供预定数据的实际时间，在存储器件的输出之间确定定时偏移。

公开(公告)号：US08161331B2

公开(公告)日：2012-04-17

申请号：US11987611

申请日：2007-12-03

申请人： Seung-jun Bae ,  Seong-jin Jang

发明人： Seung-jun Bae ,  Seong-jin Jang

IPC分类号： G06K5/04 ,  G11B20/20

CPC分类号： G11C7/1072 ,  G11C11/401 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254

摘要： A data training system and method thereof are provided. The example data training system may include a memory controller transmitting a given data pattern to a memory device, the memory controller first determining whether an error is present within the transmitted data pattern based on at least one error detection code, the at least one error detection code based on at least one of the given data pattern and the transmitted data pattern and second determining a data delay time for reducing an amount of skew based on whether the first determining step determines an error to be present within the transmitted data pattern.

摘要翻译： 提供了一种数据训练系统及其方法。 示例性数据训练系统可以包括将给定数据模式发送到存储器设备的存储器控​​制器，存储器控制器首先基于至少一个错误检测码来确定发送的数据模式内是否存在错误，该至少一个错误检测 基于给定数据模式和所发送的数据模式中的至少一个的代码，以及第二确定用于减少偏移量的数据延迟时间，基于第一确定步骤是否确定存在于所发送的数据模式中的错误。

公开(公告)号：US20080130986A1

公开(公告)日：2008-06-05

申请号：US11987611

申请日：2007-12-03

申请人： Seung-jun Bae ,  Seong-jin Jang

发明人： Seung-jun Bae ,  Seong-jin Jang

IPC分类号： G06K9/62

CPC分类号： G11C7/1072 ,  G11C11/401 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254

摘要： A data training system and method thereof are provided. The example data training system may include a memory controller transmitting a given data pattern to a memory device, the memory controller first determining whether an error is present within the transmitted data pattern based on at least one error detection code, the at least one error detection code based on at least one of the given data pattern and the transmitted data pattern and second determining a data delay time for reducing an amount of skew based on whether the first determining step determines an error to be present within the transmitted data pattern.

摘要翻译： 提供了一种数据训练系统及其方法。 示例性数据训练系统可以包括将给定数据模式发送到存储器设备的存储器控​​制器，存储器控制器首先基于至少一个错误检测码来确定发送的数据模式内是否存在错误，该至少一个错误检测 基于给定数据模式和所发送的数据模式中的至少一个的代码，以及第二确定用于减少偏移量的数据延迟时间，基于第一确定步骤是否确定存在于所发送的数据模式中的错误。

公开(公告)号：US09466393B2

公开(公告)日：2016-10-11

申请号：US14997041

申请日：2016-01-15

申请人： Jeong-kyoum Kim ,  Seok-hun Hyun ,  Jung-hwan Choi ,  Seong-jin Jang

发明人： Jeong-kyoum Kim ,  Seok-hun Hyun ,  Jung-hwan Choi ,  Seong-jin Jang

IPC分类号： G11C17/18 ,  G11C29/04 ,  G11C29/44 ,  G11C29/00 ,  G11C17/16 ,  G11C5/04 ,  G11C11/40

CPC分类号： G11C17/18 ,  G11C5/04 ,  G11C11/40 ,  G11C17/16 ,  G11C29/04 ,  G11C29/44 ,  G11C29/76 ,  G11C29/78 ,  G11C29/789 ,  G11C2029/4402

摘要： A memory device capable of rescuing defective characteristics that occur after packaging includes a memory cell array including a plurality of memory cells and an antifuse circuit unit including at least one antifuse. The antifuse circuit unit stores a defective cell address of the memory cell array in the at least one antifuse and reads the defective cell address to an external source. The antifuse circuit unit stores a defective characteristic code in the at least one antifuse, wherein the defective characteristic code is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device, and outputs the defective characteristic code to an external source.

摘要翻译： 能够拯救包装后发生的缺陷特性的存储器件包括包括多个存储单元的存储单元阵列和包括至少一个反熔丝的反熔断电路单元。 反熔丝电路单元将存储单元阵列的缺陷单元地址存储在至少一个反熔丝中，并将缺陷单元地址读取到外部源。 反熔丝电路单元将不良特性代码存储在至少一个反熔丝中，其中不良特性代码与定时参数规格，刷新规格，输入/输出（I / O）触发电压 规格和数据训练规范。 并将缺陷特征码输出到外部源。

公开(公告)号：US07499370B2

公开(公告)日：2009-03-03

申请号：US11850754

申请日：2007-09-06

申请人： Hyun-jin Kim ,  Ho-young Song ,  Youn-sik Park ,  Seong-jin Jang

发明人： Hyun-jin Kim ,  Ho-young Song ,  Youn-sik Park ,  Seong-jin Jang

IPC分类号： G11C8/00

CPC分类号： G11C7/1072 ,  G11C7/1057 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

摘要： A synchronous semiconductor memory device includes an output control signal generator, which generates an output control signal corresponding to a signal obtained by delaying a read information signal in response to a delay internal clock signal obtained by dividing an internal clock signal by n, first and second sampling signals obtained by delaying the internal clock signal, a first output control clock signal obtained by dividing the internal clock signal by n, and a column address strobe (CAS) latency signal. The synchronous semiconductor memory device also includes a data output buffer, which outputs data by buffering internal data in response to the output control signal and the first output control clock signal.

摘要翻译： 一个同步半导体存储器件包括一个输出控制信号发生器，它产生一个输出控制信号，该输出控制信号对应于通过将内部时钟信号除以n而获得的延迟内部时钟信号延迟读取信息信号获得的信号，第一和第二 通过延迟内部时钟信号获得的采样信号，通过将内部时钟信号除以n获得的第一输​​出控制时钟信号和列地址选通（CAS）等待时间信号。 同步半导体存储器件还包括数据输出缓冲器，其通过响应于输出控制信号和第一输出控制时钟信号缓冲内部数据而输出数据。

公开(公告)号：US07498853B2

公开(公告)日：2009-03-03

申请号：US11668023

申请日：2007-01-29

申请人： Seong-jin Jang

发明人： Seong-jin Jang

IPC分类号： H03K3/00

CPC分类号： H04L25/0264

摘要： Circuits, methods and systems are provided to reduce skew between a first digital signal that is transmitted by a first driver circuit over a first signal line, and a second digital signal that is transmitted by a second driver circuit over a second signal line. Skew may be reduced by sourcing or sinking additional current to or from the first signal line in response to the first digital signal and the second digital signal transitioning to opposite logical values, and otherwise refraining from sourcing or sinking the additional current to or from the first signal line. Skew may also be reduced between the first digital signal that is transmitted by the first driver circuit over the first signal line and a third digital signal that is transmitted by a third driver circuit over a third signal line by sourcing or sinking additional current to or from the first signal line in response to the first digital signal and the third digital signal transitioning to opposite logical values, and to otherwise refrain from sourcing or sinking the additional current to or from the first signal line.

摘要翻译： 提供了电路，方法和系统，以减少在第一信号线上由第一驱动电路传输的第一数字信号与由第二驱动电路在第二信号线上传输的第二数字信号之间的偏差。 响应于第一数字信号和第二数字信号转换到相反的逻辑值，可以通过向第一信号线或从第一信号线流出或吸收附加电流来减少倾斜，并且否则避免将附加电流从或从第一 信号线。 在第一信号线上由第一驱动电路发送的第一数字信号与第三数字信号之间的倾斜也可以减小，第三数字信号由第三驱动电路在第三信号线上传输， 所述第一信号线响应于所述第一数字信号和所述第三数字信号转变为相反的逻辑值，并且否则避免向或从所述第一信号线发出或吸收所述附加电流。