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公开(公告)号:US20110165734A1
公开(公告)日:2011-07-07
申请号:US12985900
申请日:2011-01-06
申请人: Seung-Woo Han , Jea-Hyuck Lee , Kyu-Sub Kwak , Kang-Ho Byun , Joon-II Kim , Duck-Hwan Kim , Kyung-Ho Park , Se-Mi Park
发明人: Seung-Woo Han , Jea-Hyuck Lee , Kyu-Sub Kwak , Kang-Ho Byun , Joon-II Kim , Duck-Hwan Kim , Kyung-Ho Park , Se-Mi Park
IPC分类号: H01L21/56
CPC分类号: H01L23/3128 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/5389 , H01L24/24 , H01L2224/12105 , H01L2224/24195 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/19105 , H01L2924/00
摘要: A manufacturing method of a semiconductor chip package includes molding a semiconductor chip and a number of passive devices after arranging on a film the semiconductor chip and the passive devices located in a vacant space around the periphery of the semiconductor chip; removing the film, forming an adhesive layer in a film-removed area, and attaching a conductive layer to the adhesive layer; etching a conductive layer to thereby form a conductive circuit pattern; and providing one or more conductive pads, which electrically connect the conductive circuit pattern to the semiconductor chip and to the passive devices.
摘要翻译: 半导体芯片封装的制造方法包括在半导体芯片和位于半导体芯片周围的空白空间中的无源器件的膜上配置半导体芯片和多个无源器件之后, 去除膜,在除膜区域中形成粘合剂层,并将导电层附着到粘合剂层上; 蚀刻导电层从而形成导电电路图案; 以及提供将导电电路图案电连接到半导体芯片和无源器件的一个或多个导电焊盘。