公开(公告)号：US07213329B2

公开(公告)日：2007-05-08

申请号：US11196243

申请日：2005-08-04

申请人： Seung-Woo Kim ,  Pyeong-Wan Kim ,  Sang-Ho Ahn ,  Bo-Seong Kim ,  Ho-Jeong Mun ,  Tae-Seong Park ,  Hee-Guk Choi

发明人： Seung-Woo Kim ,  Pyeong-Wan Kim ,  Sang-Ho Ahn ,  Bo-Seong Kim ,  Ho-Jeong Mun ,  Tae-Seong Park ,  Hee-Guk Choi

IPC分类号： H05K3/00 ,  H05K3/40 ,  H05K7/06 ,  H01L21/44

CPC分类号： H05K1/111 ,  H01L21/4853 ,  H01L23/49816 ,  H01L2224/03831 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/13007 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2924/0002 ,  H01L2924/01046 ,  H01L2924/01327 ,  H05K3/06 ,  H05K3/282 ,  H05K3/3452 ,  H05K2201/09745 ,  H05K2201/099 ,  H05K2203/0353 ,  Y02P70/611 ,  Y10T29/49124 ,  Y10T29/49147 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： In the method, a conductive pad of the board is etched to a depth that is greater than 50% and less than 100% of a thickness of the conductive pad. Subsequently, a solder ball may be formed on the etched conductive pad. For example, the conductive pad may be copper.

摘要翻译： 在该方法中，将电路板的导电焊盘蚀刻到大于导电焊盘厚度的50％且小于100％的深度。 随后，可以在蚀刻的导电焊盘上形成焊球。 例如，导电焊盘可以是铜。

公开(公告)号：US20060035453A1

公开(公告)日：2006-02-16

申请号：US11196243

申请日：2005-08-04

申请人： Seung-Woo Kim ,  Pyeong-Wan Kim ,  Sang-Ho Ahn ,  Bo-Seong Kim ,  Ho-Jeong Moon ,  Tae-Seong Park ,  Hee-Guk Choi

发明人： Seung-Woo Kim ,  Pyeong-Wan Kim ,  Sang-Ho Ahn ,  Bo-Seong Kim ,  Ho-Jeong Moon ,  Tae-Seong Park ,  Hee-Guk Choi

IPC分类号： H01L21/44 ,  H01L23/52

CPC分类号： H05K1/111 ,  H01L21/4853 ,  H01L23/49816 ,  H01L2224/03831 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/13007 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2924/0002 ,  H01L2924/01046 ,  H01L2924/01327 ,  H05K3/06 ,  H05K3/282 ,  H05K3/3452 ,  H05K2201/09745 ,  H05K2201/099 ,  H05K2203/0353 ,  Y02P70/611 ,  Y10T29/49124 ,  Y10T29/49147 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： In the method, a conductive pad of the board is etched to a depth that is greater than 50% and less than 100% of a thickness of the conductive pad. Subsequently, a solder ball may be formed on the etched conductive pad. For example, the conductive pad may be copper.

摘要翻译： 在该方法中，将电路板的导电焊盘蚀刻到大于导电焊盘厚度的50％且小于100％的深度。 随后，可以在蚀刻的导电焊盘上形成焊球。 例如，导电焊盘可以是铜。

公开(公告)号：US08234017B2

公开(公告)日：2012-07-31

申请号：US12365326

申请日：2009-02-04

申请人： Sang-Ho Ahn

发明人： Sang-Ho Ahn

IPC分类号： G01R21/06 ,  G05B15/02 ,  G06F19/00

CPC分类号： H02J13/0062 ,  G01D4/004 ,  H02J3/14 ,  H02J2003/143 ,  H02J2003/146 ,  Y02A30/62 ,  Y02B70/3266 ,  Y02B90/242 ,  Y02B90/2638 ,  Y04S20/224 ,  Y04S20/242 ,  Y04S20/322 ,  Y04S20/44 ,  Y04S40/124

摘要： The electric smart meter enabling demand response and method for the demand response are disclosed capable of acquiring an option and response information from a subscriber for enabling an active demand control, and to this end, the electric smart meter is embedded therewithin at least one or more integrated monitoring modules and includes microprocessors for transmitting a power control command to a relevant integrated monitoring module in response to a power control program based on the rate system, and controllably transmitting the measured and monitored data stored in the memory to the master server side via the communication module as well.

摘要翻译： 公开了能够从用户获取用于实现主动需求控制的选项和响应信息的能量响应的需求响应和方法的智能电表，并且为此，电智能电表被嵌入其中至少一个或多个 集成监视模块，并且包括微处理器，用于响应于基于速率系统的功率控制程序向相关的集成监控模块发送功率控制命令，并且可控地将存储在存储器中的测量和监视的数据经由主服务器侧经由 通讯模块以及。

公开(公告)号：US07012325B2

公开(公告)日：2006-03-14

申请号：US10008704

申请日：2001-12-06

申请人： Sang-Ho Ahn ,  Se-Yong Oh

发明人： Sang-Ho Ahn ,  Se-Yong Oh

IPC分类号： H01L23/02

CPC分类号： H01L23/49575 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/49503 ,  H01L23/49548 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05554 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/85001 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/48227 ,  H01L2924/3512

摘要： An ultra-thin semiconductor package includes a lead frame having a die pad and a plurality of leads surrounding the die pad. The die pad includes a chip attaching part to which a semiconductor chip is attached and a peripheral part integral with and surrounding the chip attaching part. The thickness of the chip attaching part is smaller than the thickness of the leads. The package device further includes bonding wires electrically connecting the chip to the leads, and a package body for encapsulating the semiconductor chip, bonding wires, die pad, and inner portions of the leads. A first thickness of the die pad is preferably between about 30–50% of a second thickness of the leads. An overall thickness of the package device is preferably equal to or less than 0.7 mm.

公开(公告)号：US20060049528A1

公开(公告)日：2006-03-09

申请号：US11261156

申请日：2005-10-27

申请人： In-Ku Kang ,  Sang-Ho Ahn ,  Sun-Mo Yang

发明人： In-Ku Kang ,  Sang-Ho Ahn ,  Sun-Mo Yang

IPC分类号： H01L23/52

CPC分类号： H01L24/85 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/30505 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73265 ,  H01L2224/83139 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/85399 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01047 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/0715 ,  H01L2924/0665 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554

摘要： Semiconductor chip stack structure and method are provided. A first chip has a first metal bump formed on a first electrode pad. The first chip is attached to and electrically connected to a substrate. The electrical connection is made by a bump reverse bonding method in which one end of a bonding wire is ball-bonded to the substrate and the other end is stitch-bonded to the metal bump. The second chip is stacked on the first chip. The bonding wire is substantially parallel with a top surface of the first chip. Accordingly, the chip stack structure and method minimize a space between the first chip and the second chip, thereby reducing the total height of semiconductor chip stack.

公开(公告)号：US06977439B2

公开(公告)日：2005-12-20

申请号：US10326775

申请日：2002-12-20

申请人： In-Ku Kang ,  Sang-Ho Ahn ,  Sun-Mo Yang

发明人： In-Ku Kang ,  Sang-Ho Ahn ,  Sun-Mo Yang

IPC分类号： H01L23/12 ,  H01L25/065 ,  H01L23/48 ,  H01L23/02

CPC分类号： H01L24/85 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/30505 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73265 ,  H01L2224/83139 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/85399 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01047 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/0715 ,  H01L2924/0665 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554

摘要： Semiconductor chip stack structure and method are provided. A first chip has a first metal bump formed on a first electrode pad. The first chip is attached to and electrically connected to a substrate. The electrical connection is made by a bump reverse bonding method in which one end of a bonding wire is ball-bonded to the substrate and the other end is stitch-bonded to the metal bump. The second chip is stacked on the first chip. The bonding wire is substantially parallel with a top surface of the first chip. Accordingly, the chip stack structure and method minimize a space between the first chip and the second chip, thereby reducing the total height of semiconductor chip stack.

摘要翻译： 提供半导体芯片堆叠结构和方法。 第一芯片具有形成在第一电极焊盘上的第一金属凸块。 第一芯片附接到电连接到基板。 电连接是通过凸块反向接合方法制成的，其中，接合线的一端与基板滚珠焊接，另一端与金属凸块进行针脚接合。 第二芯片堆叠在第一芯片上。 接合线基本上平行于第一芯片的顶表面。 因此，芯片堆叠结构和方法使第一芯片和第二芯片之间的空间最小化，从而降低半导体芯片堆叠的总高度。

公开(公告)号：US07253026B2

公开(公告)日：2007-08-07

申请号：US11324831

申请日：2006-01-03

申请人： Sang-Ho Ahn ,  Se-Yong Oh

发明人： Sang-Ho Ahn ,  Se-Yong Oh

IPC分类号： H01L21/48 ,  H01L21/50

CPC分类号： H01L23/49575 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/49503 ,  H01L23/49548 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05554 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/85001 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/48227 ,  H01L2924/3512

摘要： An ultra-thin semiconductor package includes a lead frame having a die pad and a plurality of leads surrounding the die pad. The die pad includes a chip attaching part to which a semiconductor chip is attached and a peripheral part integral with and surrounding the chip attaching part. The thickness of the chip attaching part is smaller than the thickness of the leads. The package device further includes bonding wires electrically connecting the chip to the leads, and a package body for encapsulating the semiconductor chip, bonding wires, die pad, and inner portions of the leads. A first thickness of the die pad is preferably between about 30-50% of a second thickness of the leads. An overall thickness of the package device is preferably equal to or less than 0.7 mm.

摘要翻译： 超薄半导体封装包括具有管芯焊盘和围绕管芯焊盘的多个引线的引线框架。 芯片焊盘包括安装半导体芯片的芯片附接部分和与芯片连接部分一体并围绕芯片连接部分的周边部分。 芯片安装部的厚度小于引线的厚度。 封装装置还包括将芯片电连接到引线的接合线，以及用于封装半导体芯片，接合线，管芯焊盘和引线的内部的封装体。 芯片焊盘的第一厚度优选在引线的第二厚度的约30-50％之间。 包装装置的整体厚度优选为0.7mm以下。

公开(公告)号：US20060110858A1

公开(公告)日：2006-05-25

申请号：US11324831

申请日：2006-01-03

申请人： Sang-Ho Ahn ,  Se-Yong Oh

发明人： Sang-Ho Ahn ,  Se-Yong Oh

IPC分类号： H01L21/50

CPC分类号： H01L23/49575 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/49503 ,  H01L23/49548 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05554 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/85001 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/48227 ,  H01L2924/3512

摘要： An ultra-thin semiconductor package includes a lead frame having a die pad and a plurality of leads surrounding the die pad. The die pad includes a chip attaching part to which a semiconductor chip is attached and a peripheral part integral with and surrounding the chip attaching part. The thickness of the chip attaching part is smaller than the thickness of the leads. The package device further includes bonding wires electrically connecting the chip to the leads, and a package body for encapsulating the semiconductor chip, bonding wires, die pad, and inner portions of the leads. A first thickness of the die pad is preferably between about 30-50% of a second thickness of the leads. An overall thickness of the package device is preferably equal to or less than 0.7 mm.

公开(公告)号：US07012259B2

公开(公告)日：2006-03-14

申请号：US10486559

申请日：2002-12-18

申请人： Sang-Hee Nam ,  Jae-Hyung Kim ,  Chi-Woong Mun ,  Hyung-won Lee ,  Sang-Ho Ahn ,  Jung-Gi Im

发明人： Sang-Hee Nam ,  Jae-Hyung Kim ,  Chi-Woong Mun ,  Hyung-won Lee ,  Sang-Ho Ahn ,  Jung-Gi Im

IPC分类号： G01T1/24

CPC分类号： H01L27/14658

摘要： A structure of a TFT substrate for a high resolution digital x-ray detector, in which two TFT substrates are arranged to be a double substrate by overlapping each other such that an upper plate is moved ½ pixel distance with respect to a lower plate in a direction along one axis. Thus, a difference in movement between the upper and lower plates is a ½ pixel distance. Also, two virtual pixels are obtained from one pixel. Three TFT substrates are arranged to be a triple substrate by overlapping one another such that a middle plate is moved a ½ pixel distance with respect to a lower plate in a direction along an X axis and an uppermost plate is arranged by being moved a ½ pixel distance with respect to the lower plate in a direction along a Y axis. Thus, resolution is increased as data of one pixel is divided into four data to be analyzed and an measured value of a pixel of each overlapping substrate is compared.

摘要翻译： 用于高分辨率数字X射线检测器的TFT基板的结构，其中两个TFT基板通过彼此重叠地布置成双重基板，使得上板相对于下板移动1/2像素距离 方向沿着一个轴。 因此，上板和下板之间的移动差异为1/2像素距离。 此外，从一个像素获得两个虚拟像素。 三个TFT基板通过彼此重叠而被布置成三重基板，使得中间板沿着X轴方向相对于下板移动1/2像素的距离，并且通过移动1/2像素来布置最上面的板 在Y轴方向上相对于下板的距离。 因此，随着一个像素的数据被分成四个要分析的数据并且比较每个重叠衬底的像素的测量值，分辨率增加。