公开(公告)号：US5841179A

公开(公告)日：1998-11-24

申请号：US704162

申请日：1996-08-28

申请人： Shekhar Pramanick ,  Bhanwar Singh ,  Che-Hoo Ng

发明人： Shekhar Pramanick ,  Bhanwar Singh ,  Che-Hoo Ng

IPC分类号： H01L21/027 ,  H01L21/768 ,  H01L31/0236

CPC分类号： H01L21/76886 ,  H01L21/0276 ,  H01L21/76888 ,  Y10S438/952

摘要： The application of a dissimilar anti-reflective coating on a conductive layer during photolithographic processing is avoided, as by modifying a portion of the upper surface of the conductive layer to exhibit anti-reflective properties. In an embodiment of the present invention, impurity ions are implanted into a portion of the upper surface of an aluminum or an aluminum-alloy conductive layer to render the upper portion substantially amorphous and, hence, decrease its reflectivity to perform an anti-reflective function.

公开(公告)号：US6087255A

公开(公告)日：2000-07-11

申请号：US127887

申请日：1998-08-03

申请人： Shekhar Pramanick ,  Bhanwar Singh ,  Che-Hoo Ng

发明人： Shekhar Pramanick ,  Bhanwar Singh ,  Che-Hoo Ng

IPC分类号： H01L21/027 ,  H01L21/768 ,  H01L31/0236

CPC分类号： H01L21/76886 ,  H01L21/0276 ,  H01L21/76888 ,  Y10S438/952

摘要： The application of a dissimilar anti-reflective coating on a conductive layer during photolithographic processing is avoided, as by modifying a portion of the upper surface of the conductive layer to exhibit anti-reflective properties. In an embodiment of the present invention, impurity ions are implanted into a portion of the upper surface of an aluminum or an aluminum-alloy conductive layer to render the upper portion substantially amorphous and, hence, decrease its reflectivity to perform an anti-reflective function.

摘要翻译： 避免了在光刻处理期间在导电层上施加不同的抗反射涂层，因为通过改变导电层的上表面的一部分以表现出抗反射性能。 在本发明的一个实施例中，杂质离子被注入到铝或铝合金导电层的上表面的一部分中，以使上部基本上是非晶的，因此降低其反射率以进行抗反射功能 。

公开(公告)号：US5876903A

公开(公告)日：1999-03-02

申请号：US774581

申请日：1996-12-31

申请人： Che-Hoo Ng ,  Bhanwar Singh ,  Shekhar Pramanick ,  Subash Gupta

发明人： Che-Hoo Ng ,  Bhanwar Singh ,  Shekhar Pramanick ,  Subash Gupta

IPC分类号： G03F7/20 ,  G03F7/40 ,  H01L21/027 ,  G03F7/26

CPC分类号： G03F7/40 ,  H01L21/0274 ,  G03F7/2024 ,  G03F7/203

摘要： A method of hardening photoresist (24) by bombardment with ionized particles (42), such as argon. Ionic bombardment causes formation of a hardened skin (22) on the exposed top (30) and side walls (32) of the photoresist (24). The hardened skin erodes at a reduced rate during etching and is less likely to react with products created during etching, thereby allowing etching of more accurate line widths and gaps.

摘要翻译： 通过用诸如氩的电离粒子（42）轰击来硬化光致抗蚀剂（24）的方法。 离子轰击导致在光致抗蚀剂（24）的暴露的顶部（30）和侧壁​​（32）上形成硬化的皮肤（22）。 硬化的皮肤在蚀刻期间以降低的速率腐蚀，并且不太可能与蚀刻期间产生的产物反应，从而允许蚀刻更精确的线宽和间隙。

公开(公告)号：US06232048B1

公开(公告)日：2001-05-15

申请号：US09260790

申请日：1999-03-01

申请人： Matthew S. Buynoski ,  Che-Hoo Ng ,  Bhanwar Singh ,  Shekhan Pramanick ,  Subhash Gupta

发明人： Matthew S. Buynoski ,  Che-Hoo Ng ,  Bhanwar Singh ,  Shekhan Pramanick ,  Subhash Gupta

IPC分类号： G03C500

CPC分类号： G03F7/40 ,  G03F7/2024 ,  G03F7/203 ,  H01L21/0274

摘要： A method of preparing a narrow photoresist line by first forming a resist pattern on a substrate, wherein a resist line is designed to have a width “w” in excess of a desired width “w1” The resist is then subjected to ionic bombardment with ionized particles in a direction normal to the planar surface of a resistant substrate. The ionic bombardment causes formation of a hardened “chemically less reactive” skin on the exposed top surface of the photoresist. The resist is then subjected to an isotropic etch procedure. Due to the hardened top surface of the narrow pattern, the side wall erode at a faster rate than the top, causing a narrowing of the line width, while retaining a more substantial photoresist thickness than would occur if the top surface would not be hardened in advance of the etch procedure.

摘要翻译： 一种通过在衬底上首先形成抗蚀剂图案来制备窄光致抗蚀剂线的方法，其中抗蚀剂线被设计成具有超过所需宽度“w1”的宽度“w”。然后将抗蚀剂用离子轰击 颗粒在垂直于耐磨基材的平坦表面的方向上。 离子轰击导致在光致抗蚀剂的暴露的顶表面上形成硬化的“化学反应性较差”的皮肤。 然后对抗蚀剂进行各向同性蚀刻程序。 由于狭窄图案的硬化顶表面，侧壁以比顶部更快的速度侵蚀，导致线宽度变窄，同时保留比如果顶表面不会硬化时更可观察到的光致抗蚀剂厚度 蚀刻过程的进步。

公开(公告)号：US08007631B2

公开(公告)日：2011-08-30

申请号：US11741991

申请日：2007-04-30

申请人： Srikanteswara Dakshina-Murthy ,  Bhanwar Singh ,  Ramkumar Subramanian

发明人： Srikanteswara Dakshina-Murthy ,  Bhanwar Singh ,  Ramkumar Subramanian

IPC分类号： C23C10/00 ,  C29C59/02 ,  C03C17/22

CPC分类号： H01L21/76817 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/31144 ,  H01L21/76811

摘要： A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold. A sequence of etches transfer and combine the via features from the first imaging layer with the trenches from the second imaging layer to create the dual damascene openings within the dielectric layer.

摘要翻译： 提供了一种系统和方法来促进与两个印记动作的双镶嵌互连集成。 该方法提供了一对包含要印制的双镶嵌图案的半透明压印模具。 该对的第一压印模具包含双镶嵌图案的通孔特征，并且该对的第二压印模具包含沟槽特征。 通孔特征压印模具与沉积在沉积在基板的电介质层上的第一转印层上的第一成像层接触。 沟槽特征压印模具与沉积在沉积在基板的第一成像层上的第二转印层上的第二成像层接触。 当每个成像层暴露于照明源时，它将以匹配相应压印模具的特征的结构固化。 一系列蚀刻将来自第一成像层的通孔特征与来自第二成像层的沟槽结合，以在介电层内形成双镶嵌开口。

公开(公告)号：US07384569B1

公开(公告)日：2008-06-10

申请号：US10909464

申请日：2004-08-02

申请人： Srikanteswara Dakshina-Murthy ,  Bhanwar Singh ,  Ramkumar Subramanian

发明人： Srikanteswara Dakshina-Murthy ,  Bhanwar Singh ,  Ramkumar Subramanian

IPC分类号： G01L21/30 ,  H01L21/00

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00

摘要： Disclosed are photolithographic systems and methods, and more particularly systems and methodologies that enhance imprint mask feature resolution. An aspect generates feedback information that facilitates control of imprint mask feature size and resolution via employing a scatterometry system to detect resolution enhancement need, and decreasing imprint mask feature size and increasing resolution of the imprint mask via a trim etch procedure.

摘要翻译： 公开了光刻系统和方法，更具体地说，增强了印迹掩模特征分辨率的系统和方法。 方面产生反馈信息，其通过采用散射测量系统来检测分辨率增强需求，以及通过修剪蚀刻程序减小压印掩模特征尺寸并增加印迹掩模的分辨率，从而有助于控制印迹掩模特征尺寸和分辨率。

公开(公告)号：US07334202B1

公开(公告)日：2008-02-19

申请号：US11145327

申请日：2005-06-03

申请人： Bhanwar Singh ,  Qiaolin Zhang ,  Iraj Emami ,  Joyce S. Oey Hewett ,  Luigi Capodiece

发明人： Bhanwar Singh ,  Qiaolin Zhang ,  Iraj Emami ,  Joyce S. Oey Hewett ,  Luigi Capodiece

IPC分类号： G06F17/50

CPC分类号： G06F17/5018 ,  G03F7/38 ,  G06F2217/80

摘要： A system for optimizing critical dimension uniformity in semiconductor manufacturing processes is provided. The system comprises a bake plate simulator to model a physical bake plate. A finite element analysis engine uses information from the bake plate simulator to calculate missing information. A lithography simulator predicts outcomes of a lithography process using information from the bake plate simulator and the finite element analysis engine. The system can be used in a predictive capacity or as part of a process control system.

摘要翻译： 提供了一种用于优化半导体制造工艺中的关键尺寸均匀性的系统。 该系统包括用于对物理烘烤板进行建模的烤盘模拟器。 有限元分析引擎使用来自烘烤板模拟器的信息来计算缺失的信息。 光刻模拟器使用来自烘烤板模拟器和有限元分析引擎的信息来预测光刻工艺的结果。 该系统可以以预测能力使用或作为过程控制系统的一部分使用。

公开(公告)号：US20070283883A1

公开(公告)日：2007-12-13

申请号：US11741991

申请日：2007-04-30

申请人： Srikanteswara Dakshina-Murthy ,  Bhanwar Singh ,  Ramkumar Subramanian

发明人： Srikanteswara Dakshina-Murthy ,  Bhanwar Singh ,  Ramkumar Subramanian

IPC分类号： C23C10/00

CPC分类号： H01L21/76817 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/31144 ,  H01L21/76811

摘要： A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold. A sequence of etches transfer and combine the via features from the first imaging layer with the trenches from the second imaging layer to create the dual damascene openings within the dielectric layer.

摘要翻译： 提供了一种系统和方法来促进与两个印记动作的双镶嵌互连集成。 该方法提供了一对包含要印制的双镶嵌图案的半透明压印模具。 该对的第一压印模具包含双镶嵌图案的通孔特征，并且该对的第二压印模具包含沟槽特征。 通孔特征压印模具与沉积在沉积在基板的电介质层上的第一转印层上的第一成像层接触。 沟槽特征压印模具与沉积在沉积在基板的第一成像层上的第二转印层上的第二成像层接触。 当每个成像层暴露于照明源时，它将以匹配相应压印模具的特征的结构固化。 一系列蚀刻将来自第一成像层的通孔特征与来自第二成像层的沟槽结合，以在介电层内形成双镶嵌开口。

公开(公告)号：US07295288B1

公开(公告)日：2007-11-13

申请号：US11000869

申请日：2004-12-01

申请人： Ramkumar Subramanian ,  Bhanwar Singh ,  Khoi A. Phan

发明人： Ramkumar Subramanian ,  Bhanwar Singh ,  Khoi A. Phan

IPC分类号： G03B27/62 ,  G03B27/02 ,  G03B27/20

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00

摘要： Systems and methodologies are provided that account for surface variations of a wafer by adjusting grating features of an imprint lithography mask. Such adjustment employs piezoelectric elements as part of the mask, which can change dimensions (e.g., a height change) and/or move when subjected to an electric voltage. Accordingly, by regulating the amount of electric voltage applied to the piezoelectric elements a controlled expansion for such elements can be obtained, to accommodate for topography variations of the wafer surface.

摘要翻译： 提供了通过调节压印光刻掩模的光栅特征来考虑晶片的表面变化的系统和方法。 这种调节使用压电元件作为掩模的一部分，其可以在经受电压时改变尺寸（例如，高度变化）和/或移动。 因此，通过调节施加到压电元件的电压量，可以获得这些元件的受控膨胀，以适应晶片表面的形貌变化。

公开(公告)号：US07235474B1

公开(公告)日：2007-06-26

申请号：US10838612

申请日：2004-05-04

申请人： Srikanteswara Dakshina-Murthy ,  Bhanwar Singh ,  Ramkumar Subramanian

发明人： Srikanteswara Dakshina-Murthy ,  Bhanwar Singh ,  Ramkumar Subramanian

IPC分类号： H01L21/44

CPC分类号： H01L21/76817 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/31144 ,  H01L21/76811

摘要： A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold. A sequence of etches transfer and combine the via features from the first imaging layer with the trenches from the second imaging layer to create the dual damascene openings within the dielectric layer.

摘要翻译： 提供了一种系统和方法来促进与两个印记动作的双镶嵌互连集成。 该方法提供了一对包含要印制的双镶嵌图案的半透明压印模具。 该对的第一压印模具包含双镶嵌图案的通孔特征，并且该对的第二压印模具包含沟槽特征。 通孔特征压印模具与沉积在沉积在基板的电介质层上的第一转印层上的第一成像层接触。 沟槽特征压印模具与沉积在沉积在基板的第一成像层上的第二转印层上的第二成像层接触。 当每个成像层暴露于照明源时，它将以匹配相应压印模具的特征的结构固化。 一系列蚀刻将来自第一成像层的通孔特征与来自第二成像层的沟槽结合，以在介电层内形成双镶嵌开口。