公开(公告)号：US5001529A

公开(公告)日：1991-03-19

申请号：US482052

申请日：1990-02-20

申请人： Shigeo Ohshima ,  Satoshi Yamano ,  Masakazu Kiryu

发明人： Shigeo Ohshima ,  Satoshi Yamano ,  Masakazu Kiryu

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06

CPC分类号： H01L27/0259

摘要： A semiconductor device is provided with a first protection path between a first terminal and an input terminal, a second protection path between a second power source terminal and the input terminal, and a third protection path between the first and the second power source terminals. Each protection path includes a first and a second P-N junction formed to be reverse biased, and is made conductive when the voltage between the corresponding two terminals exceeds a predetermined voltage so as to protect an internal circuit connected to the input terminal from an electrostatic breakdown.

公开(公告)号：US5229971A

公开(公告)日：1993-07-20

申请号：US613001

申请日：1990-11-15

申请人： Masakazu Kiryu ,  Shigeo Ohshima

发明人： Masakazu Kiryu ,  Shigeo Ohshima

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C11/407 ,  G11C11/4096

CPC分类号： G11C7/00 ,  G11C11/4096

摘要： A semiconductor memory device comprises a memory cell array, a row decoder, a column decoder, registers and a control unit. The control unit allows the write operational mode of the column decoder to switch. In the ordinary write operational mode, data in the n registers are written into the active memory cells of the n memory cell columns in on column block selected by the column decoder, respectively. In the block write mode, data in the n registers are written into active memory cells of the n memory cell columns in the 2.sup.N column blocks selected by the column decoder, respectively. Another semiconductor memory device comprises N memory units. Each memory unit comprises a memory cell array, a row decoder, a first column decoder, a second column decoder, a data input terminal, registers and a control circuit. The control circuit is operative to allow the operational mode. When the device is in the ordinary mode, data latched in the register is written into one memory cell connected to one word line selected by the row decoder of one column selected by the first column decoder of column blocks selected by the second decoder. While when the device is in the block write mode, data latched in the register is written at the same time into j memory cells connected to one word line selected by the row decoder of column blocks selected by the second column decoder.

公开(公告)号：US5075887A

公开(公告)日：1991-12-24

申请号：US647202

申请日：1991-01-28

申请人： Koichi Magome ,  Masakazu Kiryu ,  Shigeo Ohshima ,  Haruki Toda ,  Hiroshi Sahara

发明人： Koichi Magome ,  Masakazu Kiryu ,  Shigeo Ohshima ,  Haruki Toda ,  Hiroshi Sahara

IPC分类号： G11C7/00 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/409

CPC分类号： G11C7/20 ,  G11C11/4072 ,  G11C11/409 ,  G11C7/00

摘要： A semiconductor memory device is disclosed which comprises, as shown in FIG. 1, a pair of column lines, memory cells connected to the corresponding column lines, a sense amplifier connected to the column lines, row lines for selecting the memory cells in accordance with a row address signal, and first and second transistors having their current paths connected between the column lines and a fixed potential supply terminal supplied with a positive power source potential or a ground potential, wherein the gates of the first and second transistors are connected to the first and second row lines for a data rewrite operation which can be selected independently of the row line.

公开(公告)号：US4833342A

公开(公告)日：1989-05-23

申请号：US192667

申请日：1988-05-10

申请人： Masakazu Kiryu ,  Hiroyuki Koinuma ,  Kiminobu Suzuki

发明人： Masakazu Kiryu ,  Hiroyuki Koinuma ,  Kiminobu Suzuki

IPC分类号： H01L27/04 ,  G05F3/24 ,  H01L21/822 ,  H01L27/06

CPC分类号： G05F3/247

摘要： A reference potential generating circuit according to this invention includes a first insulated gate field effect transistor of an enhancement type, a second insulated gate field effect transistor of a depletion type and a voltage dividing circuit. The source of the first insulated gate field effect transistor is connected to the ground terminal, and the drain and gate thereof are connected to one another. The drain of the second insulated gate field effect transistor is connected to the power source and the gate thereof is connected to a connection node which connects the drain and gate of the first insulated gate field effect transistor. The voltage dividing circuit is connected between the drain of the first insulated gate field effect transistor and the source of the second insulated gate field effect transistor.