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    RADAR APPARATUS
    1.
    发明申请
    RADAR APPARATUS 审中-公开
    雷达装置

    公开(公告)号：US20110109495A1

    公开(公告)日：2011-05-12

    申请号：US13002065

    申请日：2010-03-19

    申请人： Shinichi Takeya ,  Kazuaki Kawabata ,  Kazuki Oosuga ,  Takuji Yoshida ,  Tomohiro Yoshida ,  Masato Niwa ,  Hideto Goto

    发明人： Shinichi Takeya ,  Kazuaki Kawabata ,  Kazuki Oosuga ,  Takuji Yoshida ,  Tomohiro Yoshida ,  Masato Niwa ,  Hideto Goto

    IPC分类号： G01S13/44

    CPC分类号： G01S13/44 ,  G01S13/34 ,  G01S13/4445 ,  G01S13/48 ,  G01S13/931

    摘要： The present invention includes: an antenna 10 including an element 11a for use in both transmission and reception that is divided into a first transmission/reception element and a second transmission/reception element, and an element 12a for reception only that is divided into a first only-reception element and a second only-reception element; a beam shaping unit 34 that divides an angle region to be observed into a plurality of regions, and forms transmission beams by using the respective elements of the antenna so that the divided angle regions are covered by the transmission beams, and in reception, sets aimed beam direction of each element of the antenna to be the same as that of the first transmission/reception element, and that of the second transmission/reception element, forms phase monopulse beam of Σ and Δ by using the first transmission/reception element and the first only-reception element, and the second transmission/reception element and the second only-reception element to cover each of the plurality of angle regions, and forms a beam with a narrow beam width by the first transmission/reception element, the second transmission/reception element, the first only-reception element, and the second only-reception element; and an angle measuring unit 37 that performs monopulse angle measurement based on the beam formed in the beam shaping unit.

    摘要翻译： 本发明包括：天线10，包括用于发送和接收的元件11a，被分为第一发送/接收元件和第二发送/接收元件;以及仅用于接收的元件12a，被分为第一 唯一接收元件和第二唯一接收元件; 光束整形单元34，其将要观察的角度区域划分为多个区域，并且通过使用天线的各个元件形成发射光束，使得分割的角度区域被发射光束覆盖，并且在接收中设置目标 天线的每个元件的波束方向与第一发送/接收元件的波束方向相同，并且第二发送/接收元件的波束方向形成＆Sgr的相位单脉冲波束; 和＆Dgr 通过使用第一发送/接收元件和第一唯一接收元件以及第二发送/接收元件和第二唯一接收元件来覆盖多个角度区域中的每一个，并且通过以下方式形成具有窄波束宽度的波束 第一发送/接收元件，第二发送/接收元件，第一唯一接收元件和第二唯一接收元件; 以及基于形成在光束整形单元中的光束进行单脉冲角测量的角度测量单元37。

    RADAR APPARATUS
    2.
    发明申请
    RADAR APPARATUS 审中-公开
    雷达装置

    公开(公告)号：US20110122013A1

    公开(公告)日：2011-05-26

    申请号：US12996058

    申请日：2010-03-19

    申请人： Shinichi Takeya ,  Kazuaki Kawabata ,  Kazuki Oosuga ,  Takuji Yoshida ,  Tomohiro Yoshida ,  Masato Niwa ,  Hideto Goto

    发明人： Shinichi Takeya ,  Kazuaki Kawabata ,  Kazuki Oosuga ,  Takuji Yoshida ,  Tomohiro Yoshida ,  Masato Niwa ,  Hideto Goto

    IPC分类号： G01S13/44 ,  G01S13/34

    CPC分类号： G01S13/584 ,  G01S3/74 ,  G01S13/44 ,  G01S2013/0263

    摘要： The present invention includes: a transmitter/receiver 20 that transmits an FMCW modulated sweep signal at least twice; an FFT unit 32 that performs Fast Fourier Transform on the at least two sweep signals received in response to the transmission from the transmitter/receiver; and an MRAV processor 35a that calculates ranges and velocities of multiple targets by calculating beat frequencies corresponding to at least two sweeps by the transmitter/receiver based on the at least two sweep signals obtained by the Fourier Transform performed by the FFT unit, calculating velocities based on a frequency difference and a time difference of the calculated beat frequencies, and calculating ranges based on the calculated velocities and beat frequencies.

    摘要翻译： 本发明包括：发送器/接收器20，其发送至少两次FMCW调制的扫描信号; FFT单元32，其对响应于来自发射机/接收机的传输而接收的至少两个扫描信号执行快速傅里叶变换; 以及MRAV处理器35a，其通过基于由FFT单元执行的傅里叶变换获得的至少两个扫描信号计算由发送器/接收器对应于至少两次扫描的拍频，来计算多个目标的范围和速度，基于计算速度 基于所计算的拍频的频率差和时间差，以及基于计算的速度和拍频来计算范围。

    Method of forming a plated layer to a predetermined thickness
    4.
    发明授权
    Method of forming a plated layer to a predetermined thickness 失效
    将镀层形成为预定厚度的方法

    公开(公告)号：US06607650B1

    公开(公告)日：2003-08-19

    申请号：US09665576

    申请日：2000-09-18

    申请人： Takayuki Niuya ,  Michihiro Ono ,  Hideto Goto ,  Kyungho Park ,  Yoshinori Marumo ,  Katsusuke Shimizu

    发明人： Takayuki Niuya ,  Michihiro Ono ,  Hideto Goto ,  Kyungho Park ,  Yoshinori Marumo ,  Katsusuke Shimizu

    IPC分类号： C25D548

    CPC分类号： H01L21/76877 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The object of the present invention is to provide a plating method capable of planarization process of high quality in comparison with the conventional plating method and also provide a plating device and a plating system adopting the plating method of the invention. In the plating method and device, an object 10 to be processed and an electrode plate 20 are dipped in a solution including objective metal ions and a forward current is supplied between the object and the electrode plate to educe a metal on the surface of the object. After forming a plating film on the object excessively, a backward current is supplied between the object 10 and the electrode 20 to uniformly remove at least part of superfluous plating film.

    摘要翻译： 本发明的目的是提供一种与传统的镀覆方法相比能够进行高质量平坦化处理的电镀方法，并且还提供了采用本发明的电镀方法的电镀装置和电镀系统。 在电镀方法和装置中，将待处理物体10和电极板20浸入包含目标金属离子的溶液中，并且在物体和电极板之间提供正向电流以在物体的表面上还原金属 。 在物体上过度地形成镀膜之后，在物体10和电极20之间提供反向电流，以均匀地去除至少一部分多余的镀膜。

    Method of manufacturing semiconductor device and manufacturing apparatus
    6.
    发明授权
    Method of manufacturing semiconductor device and manufacturing apparatus 失效
    制造半导体器件的方法和制造装置

    公开(公告)号：US06838370B1

    公开(公告)日：2005-01-04

    申请号：US09658193

    申请日：2000-09-08

    申请人： Takayuki Niuya ,  Michihiro Ono ,  Hideto Goto

    发明人： Takayuki Niuya ,  Michihiro Ono ,  Hideto Goto

    IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/321 ,  H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/02074 ,  H01L21/67028 ,  H01L21/6704 ,  H01L21/76834 ,  H01L21/7684

    摘要： The present invention is directed to suppressing the rise of a dielectric constant of insulating film during a procedure of burying wiring in semiconductor devices by using a damascene process, and it is also directed to simplifying a process of manufacturing the semiconductor devices. In terms of a process step of forming protection film on a metal layer during the damascene process, there is employed a combined arrangement of a wash unit where particles are removed from polished substrates with a processing unit where a solution containing an organic substance such as benzotriazole, which tends to be bound to the metal layers, is applied to the metal layers over the substrates after the particles are removed therefrom. For the combined arrangement of the processing unit and the wash unit, either a batch processing unit or a mono/serial processing unit can be employed.

    摘要翻译： 本发明旨在通过使用镶嵌工艺来抑制半导体器件中的布线布线过程中绝缘膜的介电常数的上升，并且还旨在简化半导体器件的制造工艺。 关于在镶嵌工艺期间在金属层上形成保护膜的工艺步骤，采用洗涤单元的组合布置，其中颗粒从抛光的基底上除去处理单元，其中含有有机物质如苯并三唑 倾向于与金属层结合的金属层在除去颗粒之后被施加到基板上的金属层上。 对于处理单元和洗涤单元的组合布置，可以采用批量处理单元或单/串行处理单元。

    Integrated circuit semiconductor device
    7.
    发明授权
    Integrated circuit semiconductor device 失效
    集成电路半导体器件

    公开(公告)号：US4761678A

    公开(公告)日：1988-08-02

    申请号：US19281

    申请日：1987-02-26

    申请人： Hideto Goto

    发明人： Hideto Goto

    IPC分类号： H01L21/76 ,  H01L21/02 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/532 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L27/02 ,  H01L29/34

    CPC分类号： H01L21/76897 ,  H01L23/5329 ,  H01L28/40 ,  H01L2924/0002

    摘要： An integrated circuit semiconductor device in which a first insulating layer including a silicon nitride film and a second insulating layer including a silicon oxide film thermally grown are formed on a major surface of a silicon substrate and contacted each other at respective side edges to form a boundary is disclosed. First and second electrodes are formed on the first and second insulating layers, respectively and separated each other with a gap. A third insulating layer fills the gap and contacts to both of peripheral surface sections of the first and second insulating layers extending from the boundary, respectively.

    摘要翻译： 一种集成电路半导体器件，其中在硅衬底的主表面上形成包括氮化硅膜的第一绝缘层和包含热生长的氧化硅膜的第二绝缘层，并在相应的侧边缘彼此接触以形成边界 被披露。 第一和第二电极分别形成在第一绝缘层和第二绝缘层上，并且间隔开。 第三绝缘层填充间隙并分别接触从边界延伸的第一和第二绝缘层的外周表面部分。

    Semiconductor device having multilayer wiring structure
    8.
    发明授权
    Semiconductor device having multilayer wiring structure 失效
    具有多层布线结构的半导体装置

    公开(公告)号：US4594606A

    公开(公告)日：1986-06-10

    申请号：US502545

    申请日：1983-06-09

    申请人： Hideto Goto ,  Haruo Amano

    发明人： Hideto Goto ,  Haruo Amano

    IPC分类号： H01L21/3213 ,  H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  H01L23/48

    CPC分类号： H01L23/5226 ,  H01L2924/0002

    摘要： A semiconductor device having a multilayer wiring structure with improved interlayer connections comprises a semiconductor substrate with a first insulating layer provided on a major surface of the substrate; a first extended wiring layer of, for example, polycrystalline silicon, formed on the first insulating layer and preferably having an essentially rectangular cross-sectional shape; a second insulating layer provided on the first insulating layer and on the first wiring layer; a contact hole provided in the second insulating layer to expose a contact region of the first wiring layer and having a width greater than the width of the contact region; a third insulating layer formed in the contact hole in contact with the sidewalls of the contact region and having a thickness which decreases in height smoothly and gradually in a direction away from the respective contact region sidewalls; a second extended wiring layer of, for example, aluminum formed on the second insulating layer, in contact with the third insulating layer in the contact hole and connected electrically to the upper surface of the contact region of the first wiring layer.

    摘要翻译： 具有改进的层间连接的多层布线结构的半导体器件包括半导体衬底，其具有设置在衬底的主表面上的第一绝缘层; 形成在第一绝缘层上，优选地具有基本上矩形的横截面形状的例如多晶硅的第一延伸布线层; 设置在所述第一绝缘层上和所述第一布线层上的第二绝缘层; 设置在所述第二绝缘层中以暴露所述第一布线层的接触区域并且具有大于所述接触区域的宽度的宽度的接触孔; 第三绝缘层，形成在与接触区域的侧壁接触的接触孔中，并且具有在远离各个接触区域侧壁的方向上平滑地逐渐降低的厚度的厚度; 第二延伸布线层，例如形成在第二绝缘层上的铝，与接触孔中的第三绝缘层接触并与第一布线层的接触区域的上表面电连接。