公开(公告)号：US06629302B2

公开(公告)日：2003-09-30

申请号：US09746886

申请日：2000-12-22

申请人： Shinji Miura ,  Yukihiro Fukumoto ,  Hirokazu Uemura ,  Yoshiyuki Saito ,  Hiroshi Ikeda ,  Takeshi Nakayama ,  Osamu Shibata ,  Shinichi Tanimoto

发明人： Shinji Miura ,  Yukihiro Fukumoto ,  Hirokazu Uemura ,  Yoshiyuki Saito ,  Hiroshi Ikeda ,  Takeshi Nakayama ,  Osamu Shibata ,  Shinichi Tanimoto

IPC分类号： G06F945

CPC分类号： G06F17/5068

摘要： A design aiding apparatus and a method, and a storage medium storing a design aiding program enable the efficient layout design of components in a multilayer wiring board formed by laminating a plurality of wiring layers. The design aiding apparatus includes (a) a first acquiring unit for acquiring information showing a first location in a lamination direction of the wiring layers, (b) a second acquiring unit for acquiring information showing a second location on a two-dimensional plane that is orthogonal to the lamination direction, and (c) a placement unit for generating information showing a space to be occupied when the component is placed in such a manner that a placement reference point of the component coincides with the second location that is on the two-dimensional plane including the first location. According to the above construction, the present invention is capable of aiding layout design of components in the wiring board.

摘要翻译： 设计辅助装置和方法以及存储设计辅助程序的存储介质使得能够通过层叠多个布线层而形成的多层布线板中的部件的有效布局设计。 设计辅助装置包括：（a）第一获取单元，用于获取表示布线层的层叠方向上的第一位置的信息，（b）第二获取单元，用于获取表示二维平面上的第二位置的信息， 与所述层叠方向正交，以及（c）放置单元，用于产生表示当所述部件以所述部件的放置基准点与所述第二位置的所述第二位置一致的方式配置时要占据的空间的信息， 包括第一位置的三维平面。 根据上述结构，本发明能够帮助布线板中部件的布局设计。

公开(公告)号：US06691296B1

公开(公告)日：2004-02-10

申请号：US09241946

申请日：1999-02-01

申请人： Takeshi Nakayama ,  Yukihiro Fukumoto ,  Yoshiyuki Saito ,  Hirokazu Uemura

发明人： Takeshi Nakayama ,  Yukihiro Fukumoto ,  Yoshiyuki Saito ,  Hirokazu Uemura

IPC分类号： G06F1750

CPC分类号： H05K3/0005 ,  G06F17/5036 ,  G06F17/5072 ,  G06F17/5077 ,  H01L2924/15192 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/115 ,  H05K2201/10689

摘要： A net detecting unit detects a set of component terminal interconnection information showing a critical net from a component terminal interconnection information list. A conductor detecting unit detects a conductor corresponding to the critical net. A component detecting unit detects two components from the set of component terminal interconnection information. A terminal detecting unit detects a power and/or ground terminal of each of the detected components. A power/ground layer detecting unit detects at least one layer, among power and ground layers, to which the detected power and/or ground terminals are connected. A layer detecting unit specifies a layer, among the detected layers, that is nearest to a signal layer on which the conductor is placed. A prohibition area generating unit generates a via prohibition area on the specified layer. As a result, vias are placed on the specified layer, avoiding the via prohibition area.

摘要翻译： 网络检测单元从组件终端互连信息列表检测表示关键网络的一组组件终端互连信息。 导体检测单元检测与关键网相对应的导体。 分量检测单元从组件端子互连信息的集合中检测两个分量。 终端检测单元检测每个检测到的组件的功率和/或接地端子。 电源/接地层检测单元检测所连接的检测到的电力和/或接地端子的功率和接地层中的至少一层。 层检测单元指定在所检测的层之中最接近放置导体的信号层的层。 禁止区域生成单元在指定的层上生成通路禁止区域。 结果，通孔被放置在指定的层上，避免了通孔禁止区域。

公开(公告)号：US5559997A

公开(公告)日：1996-09-24

申请号：US317859

申请日：1994-10-04

申请人： Masayuki Tsuchida ,  Hirokazu Uemura ,  Shinji Miura ,  Yoshiyuki Saito ,  Hiroyuki Yoshimura ,  Yuichi Nishimura ,  Nobuo Sueda

发明人： Masayuki Tsuchida ,  Hirokazu Uemura ,  Shinji Miura ,  Yoshiyuki Saito ,  Hiroyuki Yoshimura ,  Yuichi Nishimura ,  Nobuo Sueda

IPC分类号： G06F17/50 ,  H05K1/02 ,  H05K3/00

CPC分类号： G06F17/5068 ,  G06F17/5036 ,  H05K3/0005 ,  H05K1/023 ,  Y10S706/919 ,  Y10S706/92

摘要： According to the printed-circuit board of the preset invention, the circuit modification unit 120 adds a noise reduction component, based on circuit board information inputted to the design information input unit 106. Then, the layout unit 132 sets a layout after the design rule generation unit 133 generates a design rule. The rated value modification unit 124 determines rated values of noise reduction components in accordance with the layout. Thus, design rule generation, noise reduction component addition, and rated value determination are automatically performed to satisfy the electric characteristics of evaluation targets. Consequently, interactive process in designing is reduced and the efficiency of designing can be realized.

摘要翻译： 根据本发明的印刷电路板，电路修改单元120基于输入到设计信息输入单元106的电路板信息来添加噪声降低组件。然后，布局单元132在设计规则之后设置布局 生成单元133生成设计规则。 额定值修正单元124根据布局确定降噪成分的额定值。 因此，自动执行设计规则生成，降噪成分添加和额定值确定，以满足评价对象的电气特性。 因此，设计中的交互过程减少，设计效率可以实现。

公开(公告)号：US5847968A

公开(公告)日：1998-12-08

申请号：US605540

申请日：1996-02-16

申请人： Shinji Miura ,  Masayuki Tsuchida ,  Hirokazu Uemura ,  Hiroyuki Yoshimura ,  Yuichi Nishimura

发明人： Shinji Miura ,  Masayuki Tsuchida ,  Hirokazu Uemura ,  Hiroyuki Yoshimura ,  Yuichi Nishimura

IPC分类号： G06F17/50 ,  H05K13/08 ,  H02B1/24

CPC分类号： G06F17/5068

摘要： When a component is placed on a circuit board, a placement position is determined by method of elastic center. Then, it is determined whether the component was placed on the circuit board. After that, connectors are routed between the component and a design candidate component which is already placed. After that, the next component is set, and the above mentioned packaging processing is repeated.

摘要翻译： 当组件放置在电路板上时，通过弹性中心的方法确定放置位置。 然后，确定组件是否放置在电路板上。 之后，连接器在组件和已经放置的设计候选组件之间布线。 之后，设定下一个部件，重复上述的包装处理。

公开(公告)号：US5691913A

公开(公告)日：1997-11-25

申请号：US410708

申请日：1995-03-27

申请人： Masayuki Tsuchida ,  Yukinobu Nishikawa ,  Hirokazu Uemura ,  Shinji Miura

发明人： Masayuki Tsuchida ,  Yukinobu Nishikawa ,  Hirokazu Uemura ,  Shinji Miura

IPC分类号： G06F17/50 ,  H05K1/14 ,  H05K1/18 ,  H05K3/00

CPC分类号： H05K3/0005 ,  G06F17/5068 ,  H05K1/141 ,  H05K1/181

摘要： A layout designing apparatus for circuit boards including a mother board and a substrate which comprises a layout data storage unit for having areas to store data; an operation unit for giving directions; a mother board setting unit for creating the data about the mother board in the layout data storage unit according to the operation unit; a substrate placement unit for creating the data in the layout data storage unit according to the operation unit so that the substrate of a given configuration is placed on a given place on the mother board; a component placement unit for creating the data in the layout data storage unit according to the operation unit so that components of given configurations are placed on given places on the mother board and on the substrate; a routing unit for creating the data in the layout data storage unit according to the operation unit so that routing paths of given configurations are laid out on the mother board and on the substrate; a display unit; and a layout data display control unit for controlling the display unit to display configurations and places of the mother board, the substrate, components and routing paths as created.

摘要翻译： 一种包括母板和基板的电路板的布局设计装置，包括：具有用于存储数据的区域的布局数据存储单元; 用于指示的操作单元; 母板设置单元，用于根据操作单元在布局数据存储单元中创建关于母板的数据; 基板放置单元，用于根据操作单元在布局数据存储单元中创建数据，使得给定配置的基板放置在母板上的给定位置; 组件放置单元，用于根据操作单元在布局数据存储单元中创建数据，使得给定配置的组件放置在母板和基板上的给定位置; 路由单元，用于根据操作单元在布局数据存储单元中创建数据，使得给定配置的路由路径布置在母板和基板上; 显示单元; 以及布局数据显示控制单元，用于控制显示单元显示所产生的母板，基板，部件和布线路径的配置和位置。