-
公开(公告)号：US20060215468A1
公开(公告)日：2006-09-28
申请号：US11378214
申请日：2006-03-16
IPC分类号： G11C7/00
CPC分类号： G11C7/106 , G11C7/1012 , G11C7/1051 , G11C7/1066 , G11C11/5642 , G11C16/28 , G11C16/32
摘要： In a semiconductor memory device for reading out multilevel data in a time-shared manner at different timings, by providing plural control signal lines for controlling the operation timings of the output buffer circuits, the operation timings of output buffer circuits can be displaced, and the number of output buffer circuits operating simultaneously can be decreased, with the result that noise is reduced. Besides, by allowing the output buffer circuit, which outputs data read out early in a time-shared manner, to operate at an early timing, data output is terminated without retarding the operation timing of the output buffer circuit operating at the last timing.
摘要翻译： 在用于以不同定时以时间共享方式读出多电平数据的半导体存储器件中，通过提供用于控制输出缓冲电路的操作定时的多个控制信号线，输出缓冲电路的操作定时可以移位， 可以减少同时工作的输出缓冲电路的数量，从而减少噪声。 此外，通过允许以时间共享的方式早期输出数据的输出缓冲器电路以早期定时运行，数据输出终止，而不会延迟在最后定时操作的输出缓冲电路的操作定时。
-
公开(公告)号：US20050174859A1
公开(公告)日：2005-08-11
申请号：US11055641
申请日：2005-02-09
申请人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
发明人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
CPC分类号： G11C16/28 , G11C7/06 , G11C7/062 , G11C7/12 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/5004 , G11C2207/063
摘要： Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.
摘要翻译： 向所选存储单元和参考存储单元提供电流的两个偏置电路具有相同的电路结构。 每个偏置电路包括在电源节点和接合节点之间的第一有源元件，其中电流被控制以防止接合节点处的电压电平波动，电源节点和输出节点之间的第二有源元件，其中 控制电流使得输出节点处的电压电平在与其他偏置电路中的连接节点处的电压电平相反的方向上改变，第三有源元件和第四有源元件在接合节点和电流供应节点之间，以及 分别在输出节点和电流供应节点之间调整偏置电压。
-
公开(公告)号：US07301827B2
公开(公告)日：2007-11-27
申请号：US11378214
申请日：2006-03-16
IPC分类号： G11C7/00
CPC分类号： G11C7/106 , G11C7/1012 , G11C7/1051 , G11C7/1066 , G11C11/5642 , G11C16/28 , G11C16/32
摘要： In a semiconductor memory device for reading out multilevel data in a time-shared manner at different timings, by providing plural control signal lines for controlling the operation timings of the output buffer circuits, the operation timings of output buffer circuits can be displaced, and the number of output buffer circuits operating simultaneously can be decreased, with the result that noise is reduced. Besides, by allowing the output buffer circuit, which outputs data read out early in a time-shared manner, to operate at an early timing, data output is terminated without retarding the operation timing of the output buffer circuit operating at the last timing.
摘要翻译： 在用于以不同定时以时间共享方式读出多电平数据的半导体存储器件中，通过提供用于控制输出缓冲电路的操作定时的多个控制信号线，输出缓冲电路的操作定时可以移位， 可以减少同时工作的输出缓冲电路的数量，从而减少噪声。 此外，通过允许以时间共享的方式早期输出数据的输出缓冲器电路以早期定时运行，数据输出终止，而不会延迟在最后定时操作的输出缓冲电路的操作定时。
-
公开(公告)号：US07088626B2
公开(公告)日：2006-08-08
申请号：US11055641
申请日：2005-02-09
申请人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
发明人： Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
IPC分类号： G11C7/00
CPC分类号： G11C16/28 , G11C7/06 , G11C7/062 , G11C7/12 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/5004 , G11C2207/063
摘要： Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.
摘要翻译： 向所选存储单元和参考存储单元提供电流的两个偏置电路具有相同的电路结构。 每个偏置电路包括在电源节点和接合节点之间的第一有源元件，其中电流被控制以防止接合节点处的电压电平波动，电源节点和输出节点之间的第二有源元件，其中 控制电流使得输出节点处的电压电平在与其他偏置电路中的连接节点处的电压电平相反的方向上改变，第三有源元件和第四有源元件在接合节点和电流供应节点之间，以及 分别在输出节点和电流供应节点之间调整偏置电压。
-
公开(公告)号：US06930922B2
公开(公告)日：2005-08-16
申请号：US10630568
申请日：2003-07-29
CPC分类号： G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： A reading circuit, for reading data from one memory cell of a plurality of memory cells, includes a plurality of division sensing circuits each connected to the one memory cell via a sensing line corresponding thereto among a plurality of sensing lines; and a current-voltage conversion circuit for converting a current flowing through each sensing line into a sensing voltage representing a potential of the corresponding sensing line. Each division sensing circuit includes a current load circuit for supplying a current to the one memory cell via a corresponding sensing line, and a sense amplifier for sensing a potential difference between the corresponding sensing line and a corresponding reference line of a plurality of reference lines. The current load circuit included in at least one division sensing circuit has a current supply capability different from that of the current load circuit included in another division sensing circuits.
摘要翻译： 读取电路，用于从多个存储单元的一个存储单元读取数据，包括多个分割感测电路，每个分割感测电路经由多个感测线路中与之对应的感测线连接到该一个存储单元; 以及电流 - 电压转换电路，用于将流过每个感测线的电流转换成表示相应感测线的电位的感测电压。 每个分割感测电路包括用于经由相应的感测线路向一个存储单元提供电流的电流负载电路和用于感测相应感测线与多条参考线的对应参考线之间的电位差的读出放大器。 包括在至少一个分割感测电路中的电流负载电路具有与包括在另一个分割感测电路中的当前负载电路不同的电流供应能力。
-
公开(公告)号：US20110199355A1
公开(公告)日：2011-08-18
申请号：US12735930
申请日：2009-02-05
申请人： Toshio Watanabe , Shinsuke Anzai , Yoshihiro Nakatani , Hiroaki Fujino , Hirofumi Matsui , Masami Mori , Kohichi Hosokawa
发明人： Toshio Watanabe , Shinsuke Anzai , Yoshihiro Nakatani , Hiroaki Fujino , Hirofumi Matsui , Masami Mori , Kohichi Hosokawa
IPC分类号： G06F3/038
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2310/027 , G09G2310/0291 , G09G2310/0297 , G09G2330/08 , G09G2330/12
摘要： A driving circuit of at least one embodiment includes: m output terminals; m+1 video signal output sections including m+1 output circuits, respectively; a decision section for determining the quality of each of the video signal output sections; and switches for switching connections between the output terminals and the video signal output sections in accordance with a result of determination made by the decision section. When the decision section has determined the ith (i being a natural number of m or less) video signal output section to be defective, the switches connect the jth (j being a natural number of i−1 or less) video signal output section to the jth output terminal and connect the (k+1)th (k being a natural number of i or more to m or less) video signal output section to the kth output terminal. Thus provided is a driving circuit, capable of self-repairing a defective one of the video signal output sections, which has more simplified wires connected to the video signal output sections.
摘要翻译： 至少一个实施例的驱动电路包括：m个输出端子; m + 1个视频信号输出部分，分别包括m + 1个输出电路; 确定部分，用于确定每个视频信号输出部分的质量; 以及用于根据决定部分做出的确定的结果来切换输出端子和视频信号输出部分之间的连接。 当决定部分确定第i（i个m个或更少的自然数）视频信号输出部分为有缺陷时，该开关将第j个（j是i-1或更小的自然数）视频信号输出部分连接到 第j个输出端子，并将第（k + 1）（k为i以上的自然数〜m以下）视频信号输出部连接到第k个输出端子。 这样提供了一种驱动电路，其能够自我修复视频信号输出部分中的有缺陷的一个，其具有连接到视频信号输出部分的更简化的线。
-
公开(公告)号：US20050174868A1
公开(公告)日：2005-08-11
申请号：US11051139
申请日：2005-02-04
申请人： Shinsuke Anzai , Yasumichi Mori
发明人： Shinsuke Anzai , Yasumichi Mori
CPC分类号： G11C16/28 , G11C11/5642 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C16/3436 , G11C2013/0054 , G11C2213/31
摘要： A nonvolatile semiconductor memory device comprises a readout circuit which reads data stored in a selected memory cell by applying predetermined voltage to the selected memory cell and a reference cell such that currents corresponding to the respective threshold voltage may flow, and comparing the current flowing in the selected memory cell with the current flowing in the reference cell. The readout circuit commonly uses the reference cell set in the same storage state for normal readout and for readout for program verification, and when the predetermined voltage is applied to the selected memory cell and the reference memory cell at the time of the readout for the program verification, it sets an applying condition to the reference memory cell such that its storage state may be shifted more in the program state direction than that in an applying condition at the time of the normal readout.
摘要翻译： 非易失性半导体存储器件包括读出电路，其通过向所选择的存储单元施加预定电压来读取存储在所选择的存储单元中的数据，以及参考单元，使得可以流过对应于相应阈值电压的电流，并且比较流过 选定的存储单元，电流在参考单元中流动。 读出电路通常使用相同存储状态的参考单元设置用于正常读出和用于程序验证的读出，并且当在用于程序的读出时将预定电压施加到所选存储单元和参考存储单元时 验证时，将参考存储单元的应用条件设置为使得其存储状态可以在程序状态方向上比在正常读出时的应用条件中更多地移位。
-
公开(公告)号：US08587573B2
公开(公告)日：2013-11-19
申请号：US12735930
申请日：2009-02-05
申请人： Toshio Watanabe , Shinsuke Anzai , Yoshihiro Nakatani , Hiroaki Fujino , Hirofumi Matsui , Masami Mori , Kohichi Hosokawa
发明人： Toshio Watanabe , Shinsuke Anzai , Yoshihiro Nakatani , Hiroaki Fujino , Hirofumi Matsui , Masami Mori , Kohichi Hosokawa
IPC分类号： G06F3/038
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2310/027 , G09G2310/0291 , G09G2310/0297 , G09G2330/08 , G09G2330/12
摘要： A driving circuit of at least one embodiment includes: m output terminals; m+1 video signal output sections including m+1 output circuits, respectively; a decision section for determining the quality of each of the video signal output sections; and switches for switching connections between the output terminals and the video signal output sections in accordance with a result of determination made by the decision section. When the decision section has determined the ith (i being a natural number of m or less) video signal output section to be defective, the switches connect the jth (j being a natural number of i−1 or less) video signal output section to the jth output terminal and connect the (k+1)th (k being a natural number of i or more to m or less) video signal output section to the kth output terminal. Thus provided is a driving circuit, capable of self-repairing a defective one of the video signal output sections, which has more simplified wires connected to the video signal output sections.
摘要翻译： 至少一个实施例的驱动电路包括：m个输出端子; m + 1个视频信号输出部分分别包括m + 1个输出电路; 确定部分，用于确定每个视频信号输出部分的质量; 以及用于根据决定部分做出的确定的结果来切换输出端子和视频信号输出部分之间的连接。 当决定部分确定第i（i个m个或更少的自然数）视频信号输出部分为有缺陷时，该开关将第j个（j是i-1或更小的自然数）视频信号输出部分连接到 第j个输出端子，并将第（k + 1）（k为i以上的自然数〜m以下）视频信号输出部连接到第k个输出端子。 这样提供了一种驱动电路，其能够自我修复视频信号输出部分中的有缺陷的一个，其具有连接到视频信号输出部分的更简化的线。
-
公开(公告)号：US07020037B2
公开(公告)日：2006-03-28
申请号：US11051139
申请日：2005-02-04
申请人： Shinsuke Anzai , Yasumichi Mori
发明人： Shinsuke Anzai , Yasumichi Mori
IPC分类号： G11C7/02
CPC分类号： G11C16/28 , G11C11/5642 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C16/3436 , G11C2013/0054 , G11C2213/31
摘要： A nonvolatile semiconductor memory device includes a readout circuit which reads data stored in a selected memory cell by applying predetermined voltage to the selected memory cell and a reference cell such that currents corresponding to the respective threshold voltage may flow, and comparing the current flowing in the selected memory cell with the current flowing in the reference cell. The readout circuit commonly uses the reference cell set in the same storage state for normal readout and for readout for program verification, and when the predetermined voltage is applied to the selected memory cell and the reference memory cell at the time of the readout for the program verification, it sets an applying condition to the reference memory cell such that its storage state may be shifted more in the program state direction than that in an applying condition at the time of the normal readout.
摘要翻译： 非易失性半导体存储器件包括：读出电路，通过向所选择的存储单元施加预定电压，读取存储在所选择的存储单元中的数据;以及参考单元，使得与各个阈值电压相对应的电流可以流动， 选定的存储单元，电流在参考单元中流动。 读出电路通常使用相同存储状态的参考单元设置用于正常读出和用于程序验证的读出，并且当在用于程序的读出时将预定电压施加到所选择的存储单元和参考存储单元时 验证时，将参考存储单元的应用条件设置为使得其存储状态可以在程序状态方向上比在正常读出时的应用条件中更多地移位。
-
10.发明授权公开(公告)号：US08416171B2
公开(公告)日：2013-04-09
申请号：US12225182
申请日：2008-05-26
IPC分类号： G09G3/36
CPC分类号： G09G3/20 , G09G3/006 , G09G3/3648 , G09G2310/027 , G09G2310/0278 , G09G2330/08 , G09G2330/12
摘要： In one embodiment of the present invention, a liquid crystal driving semiconductor IC for driving a display panel includes an output terminal connected to the display panel, an output circuit block including a DAC circuit, and a spare output block including a DAC circuit, the DAC circuits and being connectable to the output terminal. The IC includes an op amp for comparing output signal from the DAC circuit with that of the DAC circuit, and judging circuit for judging, based on the comparison result of the op amp, whether the DAC circuit is defective, and switches and for, if the DAC circuit is defective, connecting the spare DAC circuit to the output terminal in replacement of the defective DAC circuit. This provides an IC for driving a display device, which IC has concrete measures to easily detect a defect in an output circuit, and can perform self-healing for the defect in the output circuit.
摘要翻译： 在本发明的一个实施例中，用于驱动显示面板的液晶驱动半导体IC包括连接到显示面板的输出端子，包括DAC电路的输出电路块和包括DAC电路的备用输出块，DAC 电路并可连接到输出端子。 IC包括用于比较来自DAC电路的输出信号与DAC电路的输出信号的运算放大器，以及用于基于运算放大器的比较结果判断DAC电路是否有故障的判断电路，以及用于如果 DAC电路有故障，将备用DAC电路连接到输出端子，以代替有缺陷的DAC电路。 这提供了用于驱动显示装置的IC，该IC具有能够容易地检测输出电路中的缺陷的具体措施，并且可以对输出电路中的缺陷执行自愈。
-
-
-
-
-
-
-
-
-
搜索结果
19 条记录 (耗时 0.023 秒)