-
公开(公告)号：US07903487B2
公开(公告)日：2011-03-08
申请号：US12201922
申请日：2008-08-29
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
摘要翻译： 内部电压发生器激活时，产生内部电压供给内部电路。 操作内部电压发生器消耗预定量的功率。 响应来自外部的控制信号，入口电路使内部电压发生器失活。 内部电压发生器未激活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器 记忆细胞。
-
公开(公告)号：US07869296B2
公开(公告)日：2011-01-11
申请号：US11515852
申请日：2006-09-06
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
-
公开(公告)号：US07730232B2
公开(公告)日：2010-06-01
申请号：US11113181
申请日：2005-04-25
申请人： Shinya Fujioka , Kotoku Sato , Hitoshi Ikeda , Yoshiaki Okuyama , Jun Ohno
发明人： Shinya Fujioka , Kotoku Sato , Hitoshi Ikeda , Yoshiaki Okuyama , Jun Ohno
IPC分类号： G06F13/00
CPC分类号： G06F12/0804 , G06F2212/2022 , G11C7/1006 , G11C11/406 , G11C11/40615 , G11C16/06 , G11C16/3454
摘要： A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.
摘要翻译： 提供了一种数据传输方法和系统，其防止写入闪速存储器所需的时间长度出现在表面上，作为使用闪速存储器代替SRAM的系统操作。 传送数据的方法包括以下步骤：将数据从控制器写入易失性存储器，将易失性存储器置于传送状态，将数据从传送状态的易失性存储器传送到非易失性存储器，并将易失性存储器从 响应于确认完成数据传送的传送状态。
-
公开(公告)号：US20070014178A1
公开(公告)日：2007-01-18
申请号：US11515853
申请日：2006-09-06
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
摘要翻译： 内部电压发生器激活时，产生内部电压供给内部电路。 操作内部电压发生器消耗预定量的功率。 响应来自外部的控制信号，入口电路使内部电压发生器失活。 内部电压发生器未激活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器 记忆细胞。
-
公开(公告)号：US20050259492A1
公开(公告)日：2005-11-24
申请号：US11024737
申请日：2004-12-30
申请人： Shinya Fujioka , Kotoku Sato
发明人： Shinya Fujioka , Kotoku Sato
IPC分类号： G11C11/4193 , G11C7/10 , G11C7/22 , G11C11/406 , G11C11/407 , G11C11/4195 , G11C11/4197 , G11C7/00
CPC分类号： G11C11/406 , G11C7/1039 , G11C11/40603 , G11C11/40615
摘要： A command register holding a decoded result of information relating to an access request supplied from an outside and an address register are provided, and decode of the information relating to an access request from the outside in a processing circuit, namely, a chip control circuit and an address decoder, and an operation corresponding to the external access request in a memory cell array by an access control circuit are made executable independently in parallel, whereby access requests from the outside can be inputted in multiple, and a pipelined operation can be realized for decode and an operation corresponding to the external access request in the memory cell array, thus making it possible to speed up the access operation to a semiconductor memory device without causing any problem.
摘要翻译： 提供保持与从外部提供的访问请求相关的信息的解码结果和地址寄存器的命令寄存器，并且在处理电路即芯片控制电路中解码与来自外部的访问请求有关的信息， 一个地址解码器和一个由访问控制电路对应于存储单元阵列中的外部访问请求的操作可以独立地并行执行，从而可以多次输入来自外部的访问请求，并且可以实现流水线操作 解码和对应于存储单元阵列中的外部访问请求的操作，从而使得可以加速对半导体存储器件的访问操作而不引起任何问题。
-
公开(公告)号：US20050094480A1
公开(公告)日：2005-05-05
申请号：US11001619
申请日：2004-12-02
申请人： Shinya Fujioka , Shinichi Yamada , Kotoku Sato , Jun Ohno
发明人： Shinya Fujioka , Shinichi Yamada , Kotoku Sato , Jun Ohno
IPC分类号： G11C11/401 , G11C7/10 , G11C7/22 , G11C11/4193 , G11C8/02
CPC分类号： G11C7/1018 , G11C7/22 , G11C2207/2227
摘要： A method for controlling a semiconductor memory in which mode register can be set in burst mode. To set an operation mode in burst mode, the semiconductor memory is changed first from the burst mode, through power-down mode, to standby mode of non-burst mode. Then the semiconductor memory is changed to mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.
摘要翻译： 一种用于控制可以以突发模式设置模式寄存器的半导体存储器的方法。 为了在突发模式下设置操作模式，首先将半导体存储器从突发模式（通过掉电模式）改变为非突发模式的待机模式。 然后，当以与非突发模式中使用的相同的预定顺序输入命令时，半导体存储器被改变为模式寄存器设置模式以设置模式寄存器。
-
公开(公告)号：US08130586B2
公开(公告)日：2012-03-06
申请号：US12847955
申请日：2010-07-30
IPC分类号： G11C5/14
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
摘要翻译： 内部电压发生器激活时，产生内部电压供给内部电路。 操作内部电压发生器消耗预定量的功率。 响应来自外部的控制信号，入口电路使内部电压发生器失活。 内部电压发生器未激活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器 记忆细胞。
-
8.发明授权Semiconductor memory of a dynamic random access memory (DRAM) type having a static random access memory (SRAM) interface 有权具有静态随机存取存储器（SRAM）接口的动态随机存取存储器（DRAM）类型的半导体存储器公开(公告)号：US06842391B2
公开(公告)日：2005-01-11
申请号：US10654999
申请日：2003-09-05
申请人： Shinya Fujioka , Shinichi Yamada , Kotoku Sato , Jun Ohno
发明人： Shinya Fujioka , Shinichi Yamada , Kotoku Sato , Jun Ohno
IPC分类号： G11C11/401 , G11C7/10 , G11C7/22 , G11C11/4193 , G11C7/20
CPC分类号： G11C7/1018 , G11C7/22 , G11C2207/2227
摘要： A method for controlling a semiconductor memory in which mode register can be set in burst mode. To set an operation mode in burst mode, the semiconductor memory is changed first from the burst mode, through power-down mode, to standby mode of non-burst mode. Then the semiconductor memory is changed to mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.
摘要翻译： 一种用于控制可以以突发模式设置模式寄存器的半导体存储器的方法。 为了在突发模式下设置操作模式，首先将半导体存储器从突发模式（通过掉电模式）改变为非突发模式的待机模式。 然后，当以与非突发模式中使用的相同的预定顺序输入命令时，半导体存储器被改变为模式寄存器设置模式以设置模式寄存器。
-
公开(公告)号：US20090010080A1
公开(公告)日：2009-01-08
申请号：US12201922
申请日：2008-08-29
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3268 , G06F1/3275 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C14/00 , G11C2207/2227 , G11C2211/4067 , H02M3/07 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
摘要翻译： 内部电压发生器激活时，产生内部电压供给内部电路。 操作内部电压发生器消耗预定量的功率。 响应来自外部的控制信号，入口电路使内部电压发生器失活。 内部电压发生器未激活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器 记忆细胞。
-
公开(公告)号：US07239569B2
公开(公告)日：2007-07-03
申请号：US11488785
申请日：2006-07-19
申请人： Shinya Fujioka , Kotoku Sato
发明人： Shinya Fujioka , Kotoku Sato
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/1039 , G11C11/40603 , G11C11/40615
摘要： A command register holding a decoded result of information relating to an access request supplied from an outside and an address register are provided, and decode of the information relating to an access request from the outside in a processing circuit, namely, a chip control circuit and an address decoder, and an operation corresponding to the external access request in a memory cell array by an access control circuit are made executable independently in parallel, whereby access requests from the outside can be inputted in multiple, and a pipelined operation can be realized for decode and an operation corresponding to the external access request in the memory cell array, thus making it possible to speed up the access operation to a semiconductor memory device without causing any problem.
摘要翻译： 提供保持与从外部提供的访问请求相关的信息的解码结果和地址寄存器的命令寄存器，并且在处理电路即芯片控制电路中解码与来自外部的访问请求有关的信息， 一个地址解码器和一个由访问控制电路对应于存储单元阵列中的外部访问请求的操作可以独立地并行执行，从而可以多次输入来自外部的访问请求，并且可以实现流水线操作 解码和对应于存储单元阵列中的外部访问请求的操作，从而使得可以加速对半导体存储器件的访问操作而不引起任何问题。
-
-
-
-
-
-
-
-
-
搜索结果
110 条记录 (耗时 0.027 秒)