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    Solid-state imaging device
    2.
    发明授权
    Solid-state imaging device 失效
    固态成像装置

    公开(公告)号：US4335406A

    公开(公告)日：1982-06-15

    申请号：US163298

    申请日：1980-06-26

    申请人： Shinya Ohba ,  Masaharu Kubo ,  Iwao Takemoto ,  Shoji Hanamura ,  Masakazu Aoki

    发明人： Shinya Ohba ,  Masaharu Kubo ,  Iwao Takemoto ,  Shoji Hanamura ,  Masakazu Aoki

    IPC分类号： H01L27/146 ,  H04N5/335 ,  H04N5/365 ,  H04N5/374 ,  H04N3/15

    CPC分类号： H04N5/2173

    摘要： This invention provides a signal processing circuit of a solid-state imaging device utilizing discontinuous scanning pulses having fixed interval times, and with a fixed pattern noise-eliminating circuit of high performance. In the signal processing circuit of this invention, switching elements are disposed in a feedback circuit of a signal amplifier (for example, pre-amplifier) and at an output of the signal amplifier, whereby the fixed pattern noise is suppressed so as to attain a high signal-to-noise ratio.

    摘要翻译： 本发明提供一种使用具有固定间隔时间的不连续扫描脉冲的固态成像装置的信号处理电路，以及具有高性能的固定图案噪声消除电路。 在本发明的信号处理电路中，开关元件设置在信号放大器（例如前置放大器）的反馈电路中，并在信号放大器的输出端设置，从而抑制固定图案噪声，从而达到 高信噪比。

    Interlaced solid-state imaging device
    3.
    发明授权
    Interlaced solid-state imaging device 失效
    隔行固态成像装置

    公开(公告)号：US4392158A

    公开(公告)日：1983-07-05

    申请号：US257461

    申请日：1981-04-24

    申请人： Masakazu Aoki ,  Haruhisa Ando ,  Shinya Ohba ,  Shoji Hanamura ,  Iwao Takemoto ,  Ryuichi Izawa

    发明人： Masakazu Aoki ,  Haruhisa Ando ,  Shinya Ohba ,  Shoji Hanamura ,  Iwao Takemoto ,  Ryuichi Izawa

    IPC分类号： H01L27/146 ,  H04N5/335 ,  H04N5/341 ,  H04N5/355 ,  H04N5/359 ,  H04N5/374 ,  H04N3/14

    CPC分类号： H04N3/1512 ,  H01L27/14643

    摘要： In a solid-state imaging device having a plurality of photodiodes which are arrayed in two dimensions on an identical semiconductor body, a group of horizontal switching elements and a group of vertical switching elements which pick up the photodiodes, and a horizontal scanning circuit and a vertical scanning circuit which impress scanning pulses on the horizontal and vertical switching elements respectively, and having an interlaced scanning mechanism which picks up a plurality of vertical scanning lines by means of interlace switching elements so as to permit horizontal scanning of scanning lines of a plurality of rows; a solid-state imaging device characterized in that said interlaced scanning mechanism includes insulated-gate field effect transistors for recovering voltage levels of the scanning pulses having undergone voltage drops due to the interlace switching elements.

    摘要翻译： 在具有在相同的半导体主体上二维排列的多个光电二极管的固态成像装置中，一组水平切换元件和一组拾取光电二极管的垂直开关元件，以及水平扫描电路和 垂直扫描电路，其分别在水平和垂直开关元件上施加扫描脉冲，并且具有隔行扫描机构，其通过隔行扫描开关元件拾取多条垂直扫描线，以允许水平扫描多条扫描线的扫描线 行 一种固态成像装置，其特征在于，所述隔行扫描机构包括绝缘栅场效应晶体管，用于恢复由于交错开关元件而经历电压降的扫描脉冲的电压电平。

    Solid-state imaging device
    5.
    发明授权
    Solid-state imaging device 失效
    固态成像装置

    公开(公告)号：US4268845A

    公开(公告)日：1981-05-19

    申请号：US96683

    申请日：1979-11-23

    申请人： Norio Koike ,  Shoji Hanamura ,  Masaharu Kubo

    发明人： Norio Koike ,  Shoji Hanamura ,  Masaharu Kubo

    IPC分类号： H01L27/146 ,  H04N5/335 ,  H04N5/367 ,  H04N5/372 ,  H04N5/374 ,  H01L27/14

    CPC分类号： H01L27/14643 ,  H04N5/2173

    摘要： A solid-state imaging device of a picture element construction made up of photodiodes consisting of an N-type semiconductor substrate, a P-type well region formed in the main surface of said semiconductor substrate, and an N-type region formed in said well region, and vertical switching insulated-gate field effect transistors which utilize said N-type region as either the source or the drain, characterized in that a video voltage is applied to said substrate.

    摘要翻译： 由N型半导体衬底，形成在所述半导体衬底的主表面中的P型阱区和形成在所述阱中的N型区组成的光电二极管构成的像素结构的固体摄像器件 区域和垂直开关绝缘栅场效应晶体管，其利用所述N型区域作为源极或漏极，其特征在于，将视频电压施加到所述衬底。

    Semiconductor memory device having flip-flop circuits
    6.
    发明授权
    Semiconductor memory device having flip-flop circuits 失效
    具有触发电路的半导体存储器件

    公开(公告)号：US5132771A

    公开(公告)日：1992-07-21

    申请号：US503928

    申请日：1990-04-04

    申请人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

    发明人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

    IPC分类号： G11C11/412 ,  H01L27/11

    CPC分类号： G11C11/4125 ,  H01L27/1104 ,  Y10S257/903

    摘要： A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.

    摘要翻译： 提供了具有高α射线抗扰度和高封装密度的半导体静态随机存取存储器，其也能够进行高速操作。 半导体存储器件包括每个包括触发器电路的静态随机存取存储器单元。 每个触发器电路的存储节点分别形成在夹在第一绝缘栅场效应晶体管的栅电极和第二绝缘栅场效应晶体管的栅电极之间的区域处的各pn结。 pn结的面积小于第一或第二绝缘栅场效应晶体管的沟道部分的面积。 两个第一绝缘栅场效应晶体管中的一个的栅极电极和另一个绝缘栅场效应晶体管的漏极区域以及一个绝缘栅场效应晶体管的漏极区域和另一个绝缘栅极场效应晶体管的栅极电极 另一方面，绝缘栅场效应晶体管分别通过第一和第二导电膜互相交叉耦合。 此外，为了增加封装密度并增强对软误差的抵抗力，第一和第二绝缘栅场效应晶体管的栅极彼此基本平行地延伸，并且第一和第二绝缘栅场效应晶体管的沟道区域基本上以 彼此平行。

    Process for making MOS devices for low-temperature operation
    7.
    发明授权
    Process for making MOS devices for low-temperature operation 失效
    制造用于低温操作的MOS器件的方法

    公开(公告)号：US5091325A

    公开(公告)日：1992-02-25

    申请号：US544045

    申请日：1990-06-26

    申请人： Shoji Hanamura ,  Masaaki Aoki ,  Toshiaki Masuhara

    发明人： Shoji Hanamura ,  Masaaki Aoki ,  Toshiaki Masuhara

    IPC分类号： G11C8/18 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H03K5/1534 ,  H03K19/00

    CPC分类号： H03K5/1534 ,  G11C8/18 ,  H01L27/092 ,  H01L27/10805 ,  H03K19/0016 ,  H01L27/105

    摘要： Electric charge is supplied to a circuit node being in a charge storing state within a signal processor in response to a signal-processing commencing signal. The processor is operated in a low-temperature range, for example, in the range of temperature below 200K. By this structure, a leakage current is reduced, a high degree of integration equivalent to that of a dynamic circuit can be obtained, and the simplicity of a static circuit not requiring any complicated internal/external timing signals can be realized. Also disclosed is a semiconductor device, and method of forming such semiconductor device, for operation in a range of temperatures below 100.degree. K. The device has, in a silicon surface region where the channel of the device is formed, a low impurity concentration layer (between the source and drain regions of the device). Such low impurity concentration layer is formed by evaporating amorphous silicon on a surface region of a semiconductor region of the device and passing the device through a low-temperature annealing process, the low impurity concentration layer having a lower total impurity concentration than that of the semiconductor region thereunder and having a thickness not more than 100 nm.

    Static type semiconductor memory
    8.
    发明授权
    Static type semiconductor memory 失效
    静态型半导体存储器

    公开(公告)号：US5088065A

    公开(公告)日：1992-02-11

    申请号：US593584

    申请日：1990-10-05

    申请人： Shoji Hanamura ,  Masaaki Kubotera ,  Katsuro Sasaki ,  Takao Oono ,  Kiyotsugu Ueda

    发明人： Shoji Hanamura ,  Masaaki Kubotera ,  Katsuro Sasaki ,  Takao Oono ,  Kiyotsugu Ueda

    IPC分类号： G11C7/06 ,  G11C11/419

    CPC分类号： G11C7/062 ,  G11C11/419

    摘要： Information read out from a memory cell of a static type semiconductor memory is subjected to multi-stage sense amplification in an initial stage sense amplifier, a post-stage sense amplifier and a main amplifier and then transmitted to the input of an output buffer circuit. Since an equalizing circuit is connected to the complementary inputs of each stage of the multi-stage sense amplifier, an inverse information read operation can be executed at high speed. Initially, the initial stage sense amplifier, the post-stage sense amplifier and the main amplifier are controlled to operate in high amplification gain conditions so as to execute high speed sense amplification and thereafter controlled to operate in such low power consumption conditions that the read-out information output obtained by the high speed sense amplification will not disappear.

    摘要翻译： 从静态半导体存储器的存储单元读出的信息在初级读出放大器，后级读出放大器和主放大器中进行多级感测放大，然后传输到输出缓冲电路的输入端。 由于均衡电路连接到多级读出放大器的各级的互补输入，所以可以高速执行反向信息读取操作。 最初，初级读出放大器，后级读出放大器和主放大器被控制为在高放大增益条件下工作，以便执行高速感测放大，此后被控制以在低功耗条件下工作， 通过高速感测放大获得的输出信息输出不会消失。

    Semiconductor memory device and sense amplifier
    9.
    发明授权
    Semiconductor memory device and sense amplifier 失效
    半导体存储器件和读出放大器

    公开(公告)号：US4841486A

    公开(公告)日：1989-06-20

    申请号：US946776

    申请日：1986-12-29

    申请人： Osamu Minato ,  Toshiaki Masuhara ,  Koichiro Ishibashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki

    发明人： Osamu Minato ,  Toshiaki Masuhara ,  Koichiro Ishibashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki

    IPC分类号： H01L27/11 ,  G11C7/06 ,  G11C11/416 ,  G11C11/419 ,  H01L21/8244 ,  H01L27/10

    CPC分类号： G11C11/419 ,  G11C7/062

    摘要： A semiconductor memory device having a memory plane defined by a plurality of memory cells, a decoder line for accessing the memory cells, a common data line on which a signal output from an accessed memory cell is collected, and a sense amplifier for amplifying the signal collected on the common data line. The sense amplifier has an amplifying circuit portion which is composed of a pair of common-collector type bipolar transistors supplied with the signal collected on the common data line as a differential input, and a plurality of MOS transistors for converting a change in current into a change in voltage. Each of the MOS transistors has a lightly-doped drain structure.

    摘要翻译： 一种具有由多个存储单元限定的存储器平面的半导体存储器件，用于访问存储器单元的解码器线，从所访问的存储单元输出的信号被收集的公共数据线，以及用于放大该信号的读出放大器 在公共数据线上收集。 读出放大器具有放大电路部分，该放大电路部分由一对公共集电极型双极晶体管构成，该一对公共集电极型双极晶体管被提供有作为差分输入的公共数据线上收集的信号，以及多个MOS晶体管，用于将电流变化转换为 电压变化。 每个MOS晶体管具有轻掺杂漏极结构。