公开(公告)号：US20070121761A1

公开(公告)日：2007-05-31

申请号：US11514151

申请日：2006-09-01

申请人： Shiro Dosho ,  Shiro Sakiyama ,  Yusuke Tokunaga ,  Seiji Watanabe ,  Hiroshi Koshida

发明人： Shiro Dosho ,  Shiro Sakiyama ,  Yusuke Tokunaga ,  Seiji Watanabe ,  Hiroshi Koshida

IPC分类号： H04L27/22

CPC分类号： H03K5/13 ,  H03K5/15013 ,  H03K2005/00052 ,  H03K2005/00273

摘要： A phase adjustment circuit includes first to nth two-phase adjustment circuits. Each two-phase adjustment circuit includes a first logic circuit for performing logical sum of two input signals, a second logic circuit for performing logical product of the two input signals, a first delay circuit having a signal delay equal to that of the second logic circuit and configured to delay a signal output from the first logic circuit, and a second delay circuit having a signal delay equal to that of the first logic circuit and configured to delay a signal output from the second logic circuit. Two signals output from two of the two-phase adjustment circuits in a certain stage are input into one of the two-phase adjustment circuits in the next stage.

摘要翻译： 相位调整电路包括第一至第二相位调整电路。 每个两相调节电路包括用于执行两个输入信号的逻辑和的第一逻辑电路，用于执行两个输入信号的逻辑积的第二逻辑电路，具有等于第二逻辑电路的信号延迟的信号延迟的第一延迟电路 并且被配置为延迟从第一逻辑电路输出的信号;以及第二延迟电路，其具有等于第一逻辑电路的信号延迟的信号延迟，并且被配置为延迟从第二逻辑电路输出的信号。 在一定阶段从两相调节电路中输出的两个信号在下一级输入到两相调节电路之一。

公开(公告)号：US08013650B2

公开(公告)日：2011-09-06

申请号：US11514151

申请日：2006-09-01

申请人： Shiro Dosho ,  Shiro Sakiyama ,  Yusuke Tokunaga ,  Seiji Watanabe ,  Hiroshi Koshida

发明人： Shiro Dosho ,  Shiro Sakiyama ,  Yusuke Tokunaga ,  Seiji Watanabe ,  Hiroshi Koshida

IPC分类号： H03H11/16

CPC分类号： H03K5/13 ,  H03K5/15013 ,  H03K2005/00052 ,  H03K2005/00273

摘要： A phase adjustment circuit includes first to nth two-phase adjustment circuits. Each two-phase adjustment circuit includes a first logic circuit for performing logical sum of two input signals, a second logic circuit for performing logical product of the two input signals, a first delay circuit having a signal delay equal to that of the second logic circuit and configured to delay a signal output from the first logic circuit, and a second delay circuit having a signal delay equal to that of the first logic circuit and configured to delay a signal output from the second logic circuit. Two signals output from two of the two-phase adjustment circuits in a certain stage are input into one of the two-phase adjustment circuits in the next stage.

摘要翻译： 相位调整电路包括第一至第二相位调整电路。 每个两相调节电路包括用于执行两个输入信号的逻辑和的第一逻辑电路，用于执行两个输入信号的逻辑积的第二逻辑电路，具有等于第二逻辑电路的信号延迟的信号延迟的第一延迟电路 并且被配置为延迟从第一逻辑电路输出的信号;以及第二延迟电路，其具有等于第一逻辑电路的信号延迟的信号延迟，并且被配置为延迟从第二逻辑电路输出的信号。 在一定阶段从两相调节电路中输出的两个信号在下一级输入到两相调节电路之一。

公开(公告)号：US07808295B2

公开(公告)日：2010-10-05

申请号：US12296021

申请日：2007-06-15

申请人： Shiro Sakiyama ,  Akinori Matsumoto ,  Takashi Morie ,  Shiro Dosho ,  Yusuke Tokunaga

发明人： Shiro Sakiyama ,  Akinori Matsumoto ,  Takashi Morie ,  Shiro Dosho ,  Yusuke Tokunaga

IPC分类号： H03L5/00 ,  H03F3/66

CPC分类号： H03K19/01855 ,  H03K3/0315 ,  H03K3/354

摘要： Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°

摘要翻译： n个电平移位器（LS0〜LS7）中的每一个包括用于接收n个时钟信号（P0〜P7）中的任何一个的NMOS晶体管（Mn1）和用于接收来自另一个电平移位器的输出信号的PMOS晶体管（Mp1）。 给予每个电平移位器（LS0至LS7）中的PMOS晶体管（Mp1）的输出信号是电平移位器的输出信号，其接收相对于给予NMOS的时钟信号的相位延迟量的时钟信号 包括在该电平移位器中的晶体管（Mn1）是相位量X（0°

公开(公告)号：US20090134931A1

公开(公告)日：2009-05-28

申请号：US12296021

申请日：2007-06-15

申请人： Shiro Sakiyama ,  Akinori Matsumoto ,  Takashi Morie ,  Shiro Dosho ,  Yusuke Tokunaga

发明人： Shiro Sakiyama ,  Akinori Matsumoto ,  Takashi Morie ,  Shiro Dosho ,  Yusuke Tokunaga

IPC分类号： H03L5/00

CPC分类号： H03K19/01855 ,  H03K3/0315 ,  H03K3/354

摘要： Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°

摘要翻译： n个电平移位器（LS0〜LS7）中的每一个包括用于接收n个时钟信号（P0〜P7）中的任何一个的NMOS晶体管（Mn1）和用于接收来自另一个电平移位器的输出信号的PMOS晶体管（Mp1）。 给予每个电平移位器（LS0至LS7）中的PMOS晶体管（Mp1）的输出信号是电平移位器的输出信号，其接收相对于给予NMOS的时钟信号的相位延迟量的时钟信号 包括在该电平移位器中的晶体管（Mn1）是相位量X（0°

公开(公告)号：US07920002B2

公开(公告)日：2011-04-05

申请号：US12133901

申请日：2008-06-05

申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Akinori Matsumoto ,  Takashi Morie ,  Kazuaki Sogawa ,  Yukihiro Sasagawa ,  Masaya Sumita

发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Akinori Matsumoto ,  Takashi Morie ,  Kazuaki Sogawa ,  Yukihiro Sasagawa ,  Masaya Sumita

IPC分类号： H03K5/01

CPC分类号： H03K5/00006 ,  H03K5/13

摘要： A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.

摘要翻译： n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。 电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。

公开(公告)号：US07633421B2

公开(公告)日：2009-12-15

申请号：US12093252

申请日：2007-07-30

申请人： Shiro Dosho ,  Takashi Morie ,  Yusuke Tokunaga ,  Shiro Sakiyama

发明人： Shiro Dosho ,  Takashi Morie ,  Yusuke Tokunaga ,  Shiro Sakiyama

IPC分类号： H03M1/12

CPC分类号： H03M1/123 ,  H03M1/1215 ,  H03M1/56

摘要： An A/D converter includes: a plurality of A/D conversion circuits (10 a, 10b); an input selection section (20) for selecting the A/D conversion circuit that is not executing A/D conversion to supply analog amounts obtained by sample-holding an input signal; and an output selection section (30) for selecting the A/D conversion circuit that is not executing A/D conversion to output digital amounts obtained from the selected one. Each A/D conversion circuit includes: an input memory portion (11) for sequentially storing the supplied analog amounts in a plurality of analog memory elements (111); an A/D conversion portion (12) having a plurality of A/D conversion elements (121) for converting the analog amounts stored in the analog memory elements to digital amounts; and a shift output portion (13), having a plurality of registers (131) receiving the digital amounts from the A/D conversion elements to hold the digital amounts, for shifting and outputting the digital amounts held in the registers.

摘要翻译： A / D转换器包括：多个A / D转换电路（10a，10b）; 输入选择部分（20），用于选择不执行A / D转换的A / D转换电路以提供通过采样保持输入信号获得的模拟量; 以及用于选择不执行A / D转换的A / D转换电路以输出从所选择的数字量获得的数字量的输出选择部分（30）。 每个A / D转换电路包括：用于在多个模拟存储器元件（111）中顺序地存储所提供的模拟量的输入存储器部分（11）。 具有用于将存储在模拟存储器元件中的模拟量转换为数字量的多个A / D转换元件的A / D转换部分（12） 以及移位输出部分（13），具有从A / D转换元件接收数字量以保持数字量的多个寄存器（131），用于移位和输出保存在寄存器中的数字量。

公开(公告)号：US07453313B2

公开(公告)日：2008-11-18

申请号：US11637687

申请日：2006-12-13

申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

IPC分类号： G06F3/02

CPC分类号： H02M3/07 ,  H03L7/0895 ,  H03L7/0896

摘要： A charge pumping circuit includes a first switch for controlling one of push and pull operations in accordance with a first control signal; a current mirror circuit constructed from transistors each having a different polarity from the first switch; a second switch for controlling current input to the current mirror circuit in accordance with a second control signal, the second switch being constructed from a transistor having the same characteristic as a transistor used for constructing the first switch; a first MOS capacitor one end of which is connected to an input side of the current mirror circuit; a second MOS capacitor receiving, at one end thereof, a current concerned with the push and pull operations; and a voltage buffer connected to the first and second MOS capacitors. The other of the push and pull operations is performed with an output current of the current mirror circuit.

摘要翻译： 电荷泵浦电路包括：第一开关，用于根据第一控制信号控制推挽操作中的一个; 由与所述第一开关具有不同极性的晶体管构成的电流镜电路; 第二开关，用于根据第二控制信号控制到电流镜电路的电流输入，第二开关由具有与用于构造第一开关的晶体管相同的特性的晶体管构成; 第一MOS电容器，其一端连接到电流镜电路的输入侧; 在其一端接收与推挽操作有关的电流的第二MOS电容器; 以及连接到第一和第二MOS电容器的电压缓冲器。 推挽操作中的另一个用电流镜电路的输出电流进行。

公开(公告)号：US07388405B2

公开(公告)日：2008-06-17

申请号：US11513239

申请日：2006-08-31

申请人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Makoto Hattori

发明人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Makoto Hattori

IPC分类号： H03K19/094 ,  H03K19/0175 ,  H03B1/00

CPC分类号： H03K19/018571 ,  H03F1/0261 ,  H03F3/505 ,  H03F2200/18 ,  H04L25/028

摘要： A time required for an output voltage of a source follower to rise from Low to a predetermined voltage depends on a bias voltage. Therefore, by setting a converged voltage of an output voltage to be high by increasing the bias voltage, the time required to rise up to the predetermined voltage can be reduced. Therefore, a first source follower which is biased so that the converged value of the output voltage becomes a predetermined Hi voltage when an input data signal goes from Low to Hi, and a second source follower which is biased so as to become the Hi voltage after a period of one clock when an input data signal goes from Low to Hi, are used. The two source followers are operated with appropriate timing.

摘要翻译： 源极跟随器的输出电压从低电平上升到预定电压所需的时间取决于偏置电压。 因此，通过增加偏置电压来设定输出电压的收敛电压为高，可以降低上升到预定电压所需的时间。 因此，当输入数据信号从低电平变为高电平时，被偏压使得输出电压的会聚值变为预定的Hi电压的第一源极跟随器，以及被偏置以便成为Hi电压之后的第二源极跟随器 使用输入数据信号从低电平变为高电平时的一个时钟周期。 两个来源追随者在适当的时机运行。

公开(公告)号：US20060176091A1

公开(公告)日：2006-08-10

申请号：US11289753

申请日：2005-11-30

申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/07 ,  H03L7/0891 ,  H03L7/0895

摘要： A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

摘要翻译： 延迟元件产生延迟的时钟信号，该时钟信号以基于参考时钟信号的上升（或下降）的延迟从基于环路滤波器的输出确定的延迟量转变。 信号产生电路产生根据参考时钟信号的上升和下降以及延迟的时钟信号的转变而互补地变化的两个信号。 电荷泵电路根据这两个信号执行环路滤波器，在从参考时钟信号的上升（或下降）延迟到延迟的时钟信号的转换的延迟期间进行推（或拉） （或推动）操作在从延迟的时钟信号的转变延伸到参考时钟信号的下降（或上升）的间隔期间。

公开(公告)号：US20100225518A1

公开(公告)日：2010-09-09

申请号：US12376400

申请日：2007-06-19

申请人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Kurumi Nakayama

发明人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Kurumi Nakayama

IPC分类号： H03M1/66

CPC分类号： G09G3/3685 ,  G09G3/3696 ,  G09G2310/027 ,  H03M1/76

摘要： A selection section (105) selects a step voltage, among a plurality of step voltages (SV1, SV2, SV3, . . . ) each having a voltage value changing stepwise, corresponding to the digital value of digital data (D-DATA). For each of the plurality of step voltages (SV1, SV2, SV3, . . . ), different digital values are allocated to different steps of the step voltage. An amplifier section (106) amplifies the step voltage selected by the selection section (105). An output section (107) outputs the step voltage amplified by the amplifier section (106) as an output voltage (Vout) for a time period corresponding to the digital value of the digital data (D-DATA).

摘要翻译： 选择部（105）选择与数字数据（D-DATA）的数字值对应的，具有逐步变化的电压值的多个阶梯电压（SV1，SV2，SV3 ......等）中的阶梯电压。 对于多个步进电压（SV1，SV2，SV3 ...）中的每一个，将不同的数字值分配给步进电压的不同步骤。 放大器部分（106）放大由选择部分（105）选择的步进电压。 输出部分（107）输出由放大器部分（106）放大的阶跃电压作为对应于数字数据（D-DATA）的数字值的时间周期的输出电压（Vout）。