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公开(公告)号:US20100109052A1
公开(公告)日:2010-05-06
申请号:US12608751
申请日:2009-10-29
申请人: Shizuki NAKAJIMA , Hiroyuki NAGAI , Yuji SHIRAI , Hirokazu NAKEJIMA , Chushiro KUSANO , Yu HASEGAWA , Chiko YORITA , Yasuo OSONE
发明人: Shizuki NAKAJIMA , Hiroyuki NAGAI , Yuji SHIRAI , Hirokazu NAKEJIMA , Chushiro KUSANO , Yu HASEGAWA , Chiko YORITA , Yasuo OSONE
IPC分类号: H01L27/082 , H01L27/088 , H01L21/8222 , H01L29/78
CPC分类号: H01L29/7835 , H01L21/823425 , H01L21/823475 , H01L23/66 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/17 , H01L24/28 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/16 , H01L27/088 , H01L29/04 , H01L29/0692 , H01L29/0847 , H01L29/0878 , H01L29/1087 , H01L29/41758 , H01L29/66659 , H01L29/7371 , H01L2223/6644 , H01L2223/6677 , H01L2224/0401 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05171 , H01L2224/05553 , H01L2224/05644 , H01L2224/05666 , H01L2224/1134 , H01L2224/13099 , H01L2224/13144 , H01L2224/16225 , H01L2224/16235 , H01L2224/291 , H01L2224/29111 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/04941 , H01L2924/10161 , H01L2924/10329 , H01L2924/10336 , H01L2924/12041 , H01L2924/1305 , H01L2924/1306 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/1517 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30105 , H01L2924/3011 , H01L2924/30111 , H05K1/0206 , H05K2201/09481 , H05K2201/096 , H05K2201/10674 , H01L2924/00 , H01L2924/01028 , H01L2924/01032 , H01L2924/01083 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/013
摘要: In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer.
摘要翻译: 在其中形成用于功率放大器模块的功率放大器电路的LDMOSFET元件形成的半导体芯片中,源极突起电极设置在LDMOSFET形成区域中,其中多个源极区域,多个漏极区域和多个栅极 形成用于LDMOSFET元件的电极。 源极突起电极通过源极导体层形成在主要由铝制成的源极焊盘上,该源极导体层比源焊盘厚,主要由铜制成。 在源凸起电极和源极导体层之间不设置树脂膜。
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公开(公告)号:US20100193933A1
公开(公告)日:2010-08-05
申请号:US12687311
申请日:2010-01-14
申请人: Yu HASEGAWA , Mitsuaki KATAGIRI , Satoshi ISA , Ken IWAKURA , Dai SASAKI
发明人: Yu HASEGAWA , Mitsuaki KATAGIRI , Satoshi ISA , Ken IWAKURA , Dai SASAKI
IPC分类号: H01L23/48
CPC分类号: H01L25/0657 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/48599 , H01L2224/4899 , H01L2224/49171 , H01L2224/73265 , H01L2224/85007 , H01L2224/85051 , H01L2224/85444 , H01L2225/0651 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/20755 , H01L2924/30105 , H01L2924/00 , H01L2224/48132 , H01L2924/00012 , H01L2924/20757 , H01L2924/2075 , H01L2924/20754 , H01L2224/4554 , H01L2224/85399 , H01L2224/05599
摘要: In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.
摘要翻译: 在本发明的半导体器件中,第二半导体芯片堆叠在其中心区域具有多个接合焊盘的第一半导体芯片上,其间插入有接合层。 通过穿过第一和第二半导体芯片之间的空间,分别连接到第一半导体芯片的多个接合焊盘的多条引线在第一半导体芯片的外围边缘被引出到外部。 在第一半导体芯片上的区域中设置用于保持多条电线的至少一个子集的保持构件,该区域包括通过使用不同于接合层的材料,在接合焊盘与第一半导体芯片的周边边缘之间的中间点 使得电线的子集通常位于第一半导体芯片和第二半导体芯片之间的间隔的中心。
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公开(公告)号:US20120061826A1
公开(公告)日:2012-03-15
申请号:US13192065
申请日:2011-07-27
申请人: Yu HASEGAWA , Mitsuaki KATAGIRI
发明人: Yu HASEGAWA , Mitsuaki KATAGIRI
IPC分类号: H01L23/498 , H01L23/522
CPC分类号: H01L23/49811 , H01L23/13 , H01L23/538 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/78 , H01L24/83 , H01L24/85 , H01L24/97 , H01L25/0657 , H01L2224/05554 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/4813 , H01L2224/48227 , H01L2224/4824 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/4911 , H01L2224/49175 , H01L2224/49426 , H01L2224/73215 , H01L2224/73265 , H01L2224/78301 , H01L2224/83192 , H01L2224/85051 , H01L2224/85186 , H01L2224/85203 , H01L2224/85205 , H01L2224/85207 , H01L2224/92147 , H01L2224/97 , H01L2225/0651 , H01L2225/06558 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/15311 , H01L2924/181 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2224/4554
摘要: A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.
摘要翻译: 一种器件包括衬底,半导体芯片,第一和第二焊盘以及第一布线层。 基板包括第一和第二表面。 半导体芯片包括第三和第四表面。 第三表面朝向第一表面。 第一和第二焊盘设置在第三表面上。 第一和第二焊盘彼此连接。 第一布线层设置在基板的第二表面上。 第一布线层连接到第一焊盘。
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