公开(公告)号：US06975142B2

公开(公告)日：2005-12-13

申请号：US10123251

申请日：2002-04-17

申请人： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

发明人： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC分类号： G02F1/1368 ,  G02F1/133 ,  G09G3/00 ,  G09G3/20 ,  G09G3/36 ,  G11C19/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/786 ,  H01L51/50 ,  H03K17/06 ,  H03K17/687 ,  H03K19/017 ,  H03K17/16

CPC分类号： H01L29/786 ,  H03K19/01714 ,  H03K19/01721

摘要： There is provided a semiconductor device in which fabrication steps can be reduced by constructing a circuit using only TFTs of one conductivity type and in which a voltage amplitude of an output signal can be normally obtained. A capacitance (205) is provided between a gate and a source of a TFT (203) connected to an output node, and a circuit formed of TFTs (201) and (202) has a function to bring a node a into a floating state. When the node α is in the floating state, a potential of the node a is caused higher than VDD by using gate-source capacitance coupling of the TFT (203) through the capacitance (205), thus an output signal having an amplitude of VDD-GND can be normally obtained without causing amplitude attenuation due to the threshold value of the TFT.

摘要翻译： 提供了一种半导体器件，其中可以通过仅使用一种导电类型的TFT构成电路并且可以正常获得输出信号的电压振幅来减小制造步骤。 电容（205）设置在连接到输出节点的TFT（203）的栅极和源极之间，并且由TFT（201）和（202）形成的电路具有使节点a成为浮置状态的功能 。 当节点α处于浮置状态时，通过使用TFT（203）通过电容（205）的栅极 - 源极电容耦合，使节点a的电位高于VDD，因此具有VDD的幅度的输出信号 通常可以获得-GND，而不会由于TFT的阈值引起振幅衰减。

公开(公告)号：US06928136B2

公开(公告)日：2005-08-09

申请号：US10145033

申请日：2002-05-15

申请人： Shou Nagao ,  Munehiro Azami ,  Yoshifumi Tanada

发明人： Shou Nagao ,  Munehiro Azami ,  Yoshifumi Tanada

IPC分类号： G09G3/36 ,  G11C19/00 ,  G11C19/28 ,  H03K19/017 ,  H03K19/096

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0254 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2310/0297 ,  G09G2310/08 ,  G11C19/00 ,  G11C19/28 ,  H01L2924/0002 ,  H03K19/01735 ,  H03K19/096 ,  H01L2924/00

摘要： A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD. When SP becomes low level; CK3 becomes low level; and CK1 becomes high level, the potential at the signal output section (Out) becomes low level again.

摘要翻译： 提供一种电路，其由一种导电类型的TFT构成，并且能够输出正常振幅的信号。 当输入时钟信号CK 1变为高电平时，TFT（101,103）中的每一个导通以将信号输出部分（Out）处的电位置于低电平。 然后将脉冲输入到信号输入部（In）并变为高电平。 TFT（102）的栅极电位增加到（VDD-V thN），栅极浮起来。 TFT（102）因此被导通。 然后，CK 1变为低电平，并且每个TFT（101,103）被关断。 同时，CK 3变为高电平，信号输出部分的电位增加。 同时，通过电容器（104）的功能，TFT（102）的栅极处的电位增加到等于或高于（VDD + V thN）的电平，使得出现在信号输出部分（Out ）变为等于VDD。 当SP变低时 CK 3变低; 并且CK 1变为高电平时，信号输出部（Out）的电位再次变为低电平。

公开(公告)号：US20130057161A1

公开(公告)日：2013-03-07

申请号：US13604709

申请日：2012-09-06

申请人： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

发明人： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC分类号： H05B37/02

CPC分类号： G11C19/28 ,  G02F1/13306 ,  G02F1/1333 ,  G09G3/36 ,  G09G3/3688 ,  G09G2310/0286 ,  G09G2330/021 ,  H01L27/1214 ,  H01L27/124

摘要： A pulse is input to first and second TFTs to turn ON the first and second TFTs so that the potential of a node α rises. When the potential of the node α reaches (VDD−VthN), the node α enters a floating state. Accordingly, a third TFT then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the third TFT further rises due to an operation of capacitance as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the third TFT.

摘要翻译： 脉冲被输入到第一和第二TFT以接通第一和第二TFT，使得节点α的电位上升。 当节点α的电位达到（VDD-VthN）时，节点α进入浮动状态。 因此，第三TFT然后导通，并且输出节点的电位随着时钟信号达到电平H而升高。另一方面，由于作为电位的电容的操作，第三TFT的栅电极的电位进一步上升 输出节点的电位上升，使得输出节点的电位将高于（VDD + VthN）。 因此，输出节点的电位上升到VDD而没有由第三TFT的阈值引起的电压降。

公开(公告)号：US20090322716A1

公开(公告)日：2009-12-31

申请号：US12552718

申请日：2009-09-02

申请人： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

发明人： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC分类号： G06F3/038 ,  H01L27/088 ,  H03K17/16 ,  H01L29/786 ,  H03K19/094 ,  G09G3/36

CPC分类号： H01L29/786 ,  H03K19/01714 ,  H03K19/01721

摘要： There is provided a semiconductor device in which fabrication steps can be reduced by constructing a circuit using only TFTs of one conductivity type and in which a voltage amplitude of an output signal can be normally obtained. A capacitance (205) is provided between a gate and a source of a TFT (203) connected to an output node, and a circuit formed of TFTs (201) and (202) has a function to bring a node α into a floating state. When the node α is in the floating state, a potential of the node α is caused higher than VDD by using gate-source capacitance coupling of the TFT (203) through the capacitance (205), thus an output signal having an amplitude of VDD-GND can be normally obtained without causing amplitude attenuation due to the threshold value of the TFT.

摘要翻译： 提供了一种半导体器件，其中可以通过仅使用一种导电类型的TFT构成电路并且可以正常获得输出信号的电压振幅来减小制造步骤。 电容（205）设置在连接到输出节点的TFT（203）的栅极和源极之间，并且由TFT（201）和（202）形成的电路具有使节点α成为浮置状态的功能 。 当节点α处于浮置状态时，通过使用TFT（203）通过电容（205）的栅 - 源电容耦合，使得节点α的电位高于VDD，因此具有VDD的幅度的输出信号 通常可以获得-GND，而不会由于TFT的阈值引起振幅衰减。

公开(公告)号：US07394102B2

公开(公告)日：2008-07-01

申请号：US11328456

申请日：2006-01-10

申请人： Shou Nagao ,  Munehiro Azami ,  Yoshifumi Tanada

发明人： Shou Nagao ,  Munehiro Azami ,  Yoshifumi Tanada

IPC分类号： H01L27/12

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0254 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2310/0297 ,  G09G2310/08 ,  G11C19/00 ,  G11C19/28 ,  H01L2924/0002 ,  H03K19/01735 ,  H03K19/096 ,  H01L2924/00

摘要： A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD. When SP becomes low level; CK3 becomes low level; and CK1 becomes high level, the potential at the signal output section (Out) becomes low level again.

摘要翻译： 提供一种电路，其由一种导电类型的TFT构成，并且能够输出正常振幅的信号。 当输入时钟信号CK 1变为高电平时，TFT（101,103）中的每一个导通以将信号输出部分（Out）处的电位置于低电平。 然后将脉冲输入到信号输入部（In）并变为高电平。 TFT（102）的栅极电位增加到（VDD-V thN），栅极浮起来。 TFT（102）因此被导通。 然后，CK 1变为低电平，并且每个TFT（101,103）被关断。 同时，CK 3变为高电平，信号输出部分的电位增加。 同时，通过电容器（104）的功能，TFT（102）的栅极处的电位增加到等于或高于（VDD + V thN）的电平，使得出现在信号输出部分（Out ）变为等于VDD。 当SP变低时 CK 3变低; 并且CK 1变为高电平时，信号输出部（Out）的电位再次变为低电平。

公开(公告)号：US07151278B2

公开(公告)日：2006-12-19

申请号：US10699797

申请日：2003-11-04

申请人： Shou Nagao ,  Munehiro Azami ,  Yoshifumi Tanada

发明人： Shou Nagao ,  Munehiro Azami ,  Yoshifumi Tanada

IPC分类号： H01L29/04

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0254 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2310/0297 ,  G09G2310/08 ,  G11C19/00 ,  G11C19/28 ,  H01L2924/0002 ,  H03K19/01735 ,  H03K19/096 ,  H01L2924/00

摘要： A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD. When SP becomes low level; CK3 becomes low level; and CK1 becomes high level, the potential at the signal output section (Out) becomes low level again.

摘要翻译： 提供一种电路，其由一种导电类型的TFT构成，并且能够输出正常振幅的信号。 当输入时钟信号CK 1变为高电平时，TFT（101,103）中的每一个导通以将信号输出部分（Out）处的电位置于低电平。 然后将脉冲输入到信号输入部（In）并变为高电平。 TFT（102）的栅极电位增加到（VDD-V thN），栅极浮起来。 TFT（102）因此被导通。 然后，CK 1变为低电平，并且每个TFT（101,103）被关断。 同时，CK 3变为高电平，信号输出部分的电位增加。 同时，通过电容器（104）的功能，TFT（102）的栅极处的电位增加到等于或高于（VDD + V thN）的电平，使得出现在信号输出部分（Out ）变为等于VDD。 当SP变低时 CK 3变低; 并且CK 1变为高电平时，信号输出部（Out）的电位再次变为低电平。

公开(公告)号：US20060170061A1

公开(公告)日：2006-08-03

申请号：US11328456

申请日：2006-01-10

申请人： Shou Nagao ,  Munehiro Azami ,  Yoshifumi Tanada

发明人： Shou Nagao ,  Munehiro Azami ,  Yoshifumi Tanada

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0254 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2310/0297 ,  G09G2310/08 ,  G11C19/00 ,  G11C19/28 ,  H01L2924/0002 ,  H03K19/01735 ,  H03K19/096 ,  H01L2924/00

摘要： A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD. When SP becomes low level; CK3 becomes low level; and CK1 becomes high level, the potential at the signal output section (Out) becomes low level again.

公开(公告)号：US07710384B2

公开(公告)日：2010-05-04

申请号：US11420404

申请日：2006-05-25

申请人： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

发明人： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC分类号： G09G3/36

CPC分类号： G11C19/28 ,  G02F1/13306 ,  G02F1/1333 ,  G09G3/36 ,  G09G3/3688 ,  G09G2310/0286 ,  G09G2330/021 ,  H01L27/1214 ,  H01L27/124

摘要： A drive circuit of a display device, which comprise only single conductive TFTs and in which amplitude of an output signal is normal, is provided.A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node á rises. When the potential of the node á reaches (VDD−VthN), the node á became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105. An output at the subsequent stage is then inputted to TFTs 102 and 103 to turn the TFTs 102 and 103 ON, while the potential of the node á drops down to turn the TFT 105 OFF. A TFT 106 turns ON at the same time so that the potential of the output node would reach the level L.

摘要翻译： 提供了仅包括单个导电TFT并且输出信号的幅度正常的显示装置的驱动电路。 脉冲被输入到TFT 101和104，使得TFT将导通，然后节点á的电位升高。 当节点á的电位达到（VDD-VthN）时，节点á变为浮动状态。 因此，TFT 105然后导通，并且输出节点的电位随着时钟信号达到电平H而上升。另一方面，由于电容107的操作，TFT 105的栅电极的电位进一步上升， 输出节点的电位上升，使得输出节点的电位将高于（VDD + VthN）。 因此，输出节点的电位上升到VDD而没有由TFT105的阈值引起的电压降。然后，后级的输出被输入到TFT 102和103，以使TFT 102和103接通，同时 节点á下降以关闭TFT 105。 TFT 106同时导通，使得输出节点的电位达到电平L.

公开(公告)号：US20100073348A1

公开(公告)日：2010-03-25

申请号：US12575642

申请日：2009-10-08

申请人： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

发明人： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC分类号： G06F3/038

CPC分类号： G11C19/28 ,  G02F1/13306 ,  G02F1/1333 ,  G09G3/36 ,  G09G3/3688 ,  G09G2310/0286 ,  G09G2330/021 ,  H01L27/1214 ,  H01L27/124

摘要： A drive circuit of a display device, which comprise only single conductive TFTs and in which amplitude of an output signal is normal, is provided.A pulse is inputted to TFTs 101 and 104 so that the TFTs would turn ON and then potential of a node á rises. When the potential of the node á reaches (VDD−VthN), the node á became in a floating state. Accordingly, a TFT 105 then turns ON, and potential of an output node rises as a clock signal reaches the level H. On the other hand, potential of a gate electrode of the TFT 105 further rises due to an operation of capacitance 107 as the potential of the output node rises, so that the potential of the output node would be higher than (VDD+VthN). Thus, the potential of the output node rises to VDD without voltage drop caused by a threshold of the TFT 105. An output at the subsequent stage is then inputted to TFTs 102 and 103 to turn the TFTs 102 and 103 ON, while the potential of the node á drops down to turn the TFT 105 OFF. A TFT 106 turns ON at the same time so that the potential of the output node would reach the level L.

摘要翻译： 提供了仅包括单个导电TFT并且输出信号的幅度正常的显示装置的驱动电路。 脉冲被输入到TFT 101和104，使得TFT将导通，然后节点á的电位升高。 当节点á的电位达到（VDD-VthN）时，节点á变为浮动状态。 因此，TFT 105然后导通，并且输出节点的电位随着时钟信号达到电平H而上升。另一方面，由于电容107的操作，TFT 105的栅电极的电位进一步上升， 输出节点的电位上升，使得输出节点的电位将高于（VDD + VthN）。 因此，输出节点的电位上升到VDD而没有由TFT105的阈值引起的电压降。然后，后级的输出被输入到TFT 102和103，以使TFT 102和103接通，同时 节点á下降以关闭TFT 105。 TFT 106同时导通，使得输出节点的电位达到电平L.

公开(公告)号：US07586478B2

公开(公告)日：2009-09-08

申请号：US11270647

申请日：2005-11-10

申请人： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

发明人： Munehiro Azami ,  Shou Nagao ,  Yoshifumi Tanada

IPC分类号： G09G3/36 ,  H03K19/0175

CPC分类号： H01L29/786 ,  H03K19/01714 ,  H03K19/01721

摘要： There is provided a semiconductor device in which fabrication steps can be reduced by constructing a circuit using only TFTs of one conductivity type and in which a voltage amplitude of an output signal can be normally obtained. A capacitance (205) is provided between a gate and a source of a TFT (203) connected to an output node, and a circuit formed of TFTs (201) and (202) has a function to bring a node α into a floating state. When the node α is in the floating state, a potential of the node α is caused higher than VDD by using gate-source capacitance coupling of the TFT (203) through the capacitance (205), thus an output signal having an amplitude of VDD-GND can be normally obtained without causing amplitude attenuation due to the threshold value of the TFT.

摘要翻译： 提供了一种半导体器件，其中可以通过仅使用一种导电类型的TFT构成电路并且可以正常获得输出信号的电压振幅来减小制造步骤。 电容（205）设置在连接到输出节点的TFT（203）的栅极和源极之间，并且由TFT（201）和（202）形成的电路具有使节点α成为浮置状态的功能 。 当节点α处于浮置状态时，通过使用TFT（203）通过电容（205）的栅 - 源电容耦合，使得节点α的电位高于VDD，因此具有VDD的幅度的输出信号 通常可以获得-GND，而不会由于TFT的阈值引起振幅衰减。