公开(公告)号：US20080191286A1

公开(公告)日：2008-08-14

申请号：US11972601

申请日：2008-01-10

申请人： Shou-Zen Chang ,  Hong Yu Yu ,  Anabela Veloso ,  Rita Vos ,  Stefan Kubicek ,  Serge Biesemans ,  Raghunath Singanamalla ,  Anne Lauwers ,  Bart Onsia

发明人： Shou-Zen Chang ,  Hong Yu Yu ,  Anabela Veloso ,  Rita Vos ,  Stefan Kubicek ,  Serge Biesemans ,  Raghunath Singanamalla ,  Anne Lauwers ,  Bart Onsia

IPC分类号： H01L27/00 ,  H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L29/785

摘要： The present disclosure provides a dual workfunction semiconductor device and a method for manufacturing a dual workfunction semiconductor device. The method comprises providing a device on a first region and a device on a second region of a substrate. According to embodiments described herein, the method includes providing a dielectric layer onto the first and second region of the substrate, the dielectric layer on the first region being integrally deposited with the dielectric layer on the second region, and providing a gate electrode on top of the dielectric layer on both the first and second regions, the gate electrode on the first region being integrally deposited with the gate electrode on the second region. The method further includes changing the workfunction of the device on the first region by providing a capping layer onto the first region between the dielectric layer and the gate electrode, and changing the workfunction of the device on the second region by including species at the interface between the dielectric layer and the electrode.

摘要翻译： 本公开提供了一种双功能半导体器件和用于制造双功能半导体器件的方法。 该方法包括在第一区域上提供器件和在衬底的第二区域上提供器件。 根据本文所述的实施例，该方法包括在基板的第一和第二区域上提供介电层，第一区域上的电介质层与第二区域上的电介质层整体沉积，并且在 所述第一区域和所述第二区域上的所述电介质层，所述第一区域上的所述栅电极与所述第二区域上的所述栅极电极整体地沉积。 该方法还包括通过在介电层和栅电极之间的第一区域上设置覆盖层来改变第一区域上的器件的功函数，以及通过在第二区域上的界面处包括物质来改变第二区域上的器件的功函数 介电层和电极。

公开(公告)号：US08643121B2

公开(公告)日：2014-02-04

申请号：US13143762

申请日：2009-11-23

申请人： Markus Mueller ,  Raghunath Singanamalla

发明人： Markus Mueller ,  Raghunath Singanamalla

IPC分类号： H01L21/70

CPC分类号： H01L29/4983 ,  H01L21/26586 ,  H01L29/78

摘要： A semiconductor device and a method of manufacturing a gate stack for such a semiconductor device. The device includes a gate stack that has a gate insulation layer provided over a channel region of the device, and a metal layer that is insulated from the channel region by the gate insulation layer. The metal layer contains work function modulating impurities which have a concentration profile that varies along a length of the metal layer from the source region to the drain region. The gate stack has a first effective work function in the vicinity of a source region and/or the drain region of the device and a second, different effective work function toward a center of the channel region.

摘要翻译： 半导体器件及其制造方法。 该器件包括栅极堆叠，其具有设置在器件的沟道区域上的栅极绝缘层，以及通过栅极绝缘层与沟道区域绝缘的金属层。 金属层包含调制杂质的功函数，这些杂质具有沿着金属层从源极区域到漏极区域的长度变化的浓度分布。 栅极堆叠在器件的源极区域和/或漏极区域附近具有第一有效功函数，以及朝向沟道区域的中心的第二有效功函数。

公开(公告)号：US20110049634A1

公开(公告)日：2011-03-03

申请号：US12935760

申请日：2009-03-30

申请人： Raghunath Singanamalla ,  Jacob C. Hooker ,  Marcus J. H. Van Dal

发明人： Raghunath Singanamalla ,  Jacob C. Hooker ,  Marcus J. H. Van Dal

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/82345 ,  H01L21/265 ,  H01L21/28097 ,  H01L21/823842 ,  H01L29/4975

摘要： A method of manufacturing a semiconductor device having gate electrodes of a suitable work function material is disclosed. The method comprises providing a substrate (100) including a number of active regions (110, 120) and a dielectric layer (130) covering the active regions (110, 120), and forming a stack of layers (140, 150, 160) over the dielectric layer. The formation of the stack of layers comprises depositing a first metal layer (140), having a first thickness, e.g. less than 10 nm, over the dielectric layer (130), depositing a second metal layer (150) having a second thickness over the first metal layer (140), the second thickness being larger than the first thickness, introducing a dopant (152, 154) into the second metal layer (150), exposing the device to an increased temperature to migrate at least some of the dopant (152, 154) from the second metal layer (150) beyond the interface between the first metal layer (140) and the second metal layer (150); and patterning the stack into a number of gate electrodes (170). This way a gate electrode is formed having an dopant profile in the vicinity of the dielectric layer (130) such that the work function of the gate electrode is optimized, without the gate dielectric suffering from degradation by dopant penetration.

摘要翻译： 公开了一种制造具有合适功函材料的栅极的半导体器件的方法。 该方法包括提供包括多个有源区（110,120）和覆盖有源区（110,120）的介电层（130）的衬底（100），以及形成层叠层（140,150,160） 在介电层上。 堆叠层的形成包括沉积具有第一厚度的第一金属层（140） 在所述电介质层（130）上方小于10nm，在所述第一金属层（140）上沉积具有第二厚度的第二金属层（150），所述第二厚度大于所述第一厚度， 154）插入到第二金属层（150）中，使该器件暴露于升高的温度以将来自第二金属层（150）的至少一些掺杂剂（152,154）从第一金属层（140） 和第二金属层（150）; 以及将所述堆叠图案化成多个栅电极（170）。 这样，在电介质层（130）附近形成具有掺杂剂分布的栅电极，使得优化栅电极的功函数，而不会使掺杂剂渗透的栅电介质劣化。

公开(公告)号：US08766370B2

公开(公告)日：2014-07-01

申请号：US12645905

申请日：2009-12-23

申请人： Jacob Christopher Hooker ,  Raghunath Singanamalla ,  Jasmine Petry

发明人： Jacob Christopher Hooker ,  Raghunath Singanamalla ,  Jasmine Petry

IPC分类号： H01L21/70

CPC分类号： H01L21/823857 ,  H01L21/28079 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/495 ,  H01L29/517

摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate having a first region and a second region, a pMOS transistor formed over the first region and an nMOS formed over the second region. The pMOS transistor has a gate structure that includes: an interfacial layer formed over the substrate; a AlOx layer formed over the interfacial layer; and a metal layer including Mo or W formed over the AlOx layer. The nMOS transistor has a gate structure that includes: the interfacial layer formed over the substrate; a DyOx layer formed over the interfacial layer; and the metal layer including Mo or W formed over the DyOx layer.

摘要翻译： 本公开提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域上形成的pMOS晶体管和在第二区域上形成的nMOS。 pMOS晶体管具有栅极结构，其包括：在衬底上形成的界面层; 在界面层上形成AlOx层; 以及在AlOx层上形成包括Mo或W的金属层。 nMOS晶体管具有栅极结构，其包括：在衬底上形成的界面层; 在界面层上形成DyOx层; 并且在DyOx层上形成包括Mo或W的金属层。

公开(公告)号：US20110291206A1

公开(公告)日：2011-12-01

申请号：US13143762

申请日：2009-11-23

申请人： Markus Mueller ,  Raghunath Singanamalla

发明人： Markus Mueller ,  Raghunath Singanamalla

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L29/4983 ,  H01L21/26586 ,  H01L29/78

摘要： A semiconductor device and a method of manufacturing a gate stack for such a semiconductor device. The device includes a gate stack that has a gate insulation layer provided over a channel region of the device, and a metal layer that is insulated from the channel region by the gate insulation layer. The metal layer contains work function modulating impurities which have a concentration profile that varies along a length of the metal layer from the source region to the drain region. The gate stack has a first effective work function in the vicinity of a source region and/or the drain region of the device and a second, different effective work function toward a centre of the channel region.

摘要翻译： 半导体器件及其制造方法。 该器件包括栅极堆叠，其具有设置在器件的沟道区域上的栅极绝缘层，以及通过栅极绝缘层与沟道区域绝缘的金属层。 金属层包含调制杂质的功函数，这些杂质具有沿着金属层从源极区域到漏极区域的长度变化的浓度分布。 栅极堆叠在器件的源极区域和/或漏极区域附近具有第一有效功函数，以及朝向沟道区域的中心的第二有效功函数。

公开(公告)号：US20110095376A1

公开(公告)日：2011-04-28

申请号：US12645905

申请日：2009-12-23

申请人： Jacob Christopher Hooker ,  Raghunath Singanamalla ,  Jasmine Petry

发明人： Jacob Christopher Hooker ,  Raghunath Singanamalla ,  Jasmine Petry

IPC分类号： H01L27/092 ,  H01L21/28

CPC分类号： H01L21/823857 ,  H01L21/28079 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/495 ,  H01L29/517

摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate having a first region and a second region, a pMOS transistor formed over the first region and an nMOS formed over the second region. The pMOS transistor has a gate structure that includes: an interfacial layer formed over the substrate; a AlOx layer formed over the interfacial layer; and a metal layer including Mo or W formed over the AlOx layer. The nMOS transistor has a gate structure that includes: the interfacial layer formed over the substrate; a DyOx layer formed over the interfacial layer; and the metal layer including Mo or W formed over the DyOx layer.

摘要翻译： 本公开提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域上形成的pMOS晶体管和在第二区域上形成的nMOS。 pMOS晶体管具有栅极结构，其包括：在衬底上形成的界面层; 在界面层上形成AlOx层; 以及在AlOx层上形成包括Mo或W的金属层。 nMOS晶体管具有栅极结构，其包括：在衬底上形成的界面层; 在界面层上形成DyOx层; 并且在DyOx层上形成包括Mo或W的金属层。

公开(公告)号：US20080197421A1

公开(公告)日：2008-08-21

申请号：US11896164

申请日：2007-08-30

申请人： Riichiro Mitsuhashi ,  Raghunath Singanamalla

发明人： Riichiro Mitsuhashi ,  Raghunath Singanamalla

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L21/82345 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/092

摘要： A semiconductor device includes a p-type active region and an n-type active region which are formed in a semiconductor substrate and a p-type MISFET including a gate insulating film formed on the p-type active region and a first gate electrode including a first electrode formation film of which upper part has a concentration of La higher than the other part thereof. The semiconductor device further includes an n-type MISFET including a gate insulating film formed on the n-type active region and a second gate electrode including a second electrode formation film of which upper part has a concentration of Al higher than the other part thereof.

摘要翻译： 半导体器件包括形成在半导体衬底中的p型有源区和n型有源区，以及包括形成在p型有源区上的栅极绝缘膜的p型MISFET和包括 第一电极形成膜的上部具有比其他部分高的La的浓度。 半导体器件还包括n型MISFET，其包括形成在n型有源区上的栅极绝缘膜和第二栅电极，第二栅极包括第二电极形成膜，其上部的浓度比其他部分高。