公开(公告)号：US20120111607A1

公开(公告)日：2012-05-10

申请号：US13354438

申请日：2012-01-20

申请人： Shuhichi OKABE ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

发明人： Shuhichi OKABE ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC分类号： H05K1/02

CPC分类号： H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

摘要： A circuit board including: an insulator having a trench; a first circuit pattern formed to bury a portion of the trench; and a second circuit pattern formed on a surface of the insulator having the trench formed therein.

摘要翻译： 一种电路板，包括：具有沟槽的绝缘体; 形成为埋入沟槽的一部分的第一电路图案; 以及形成在其中形成有沟槽的绝缘体的表面上的第二电路图案。

公开(公告)号：US20080264676A1

公开(公告)日：2008-10-30

申请号：US11976207

申请日：2007-10-22

申请人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

发明人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC分类号： H05K1/00

CPC分类号： H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

摘要： A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator.

摘要翻译： 一种电路板的制造方法，其特征在于，包括：在堆叠在载体上的种子层上，形成导电消除图案，所述导电解像图案包括依次与第一电路图案对应地层叠的第一镀层，第一金属层和第二镀层 ; 将载体和绝缘体堆叠并压在一起，使得具有导电缓冲图案的载体的表面面向绝缘体; 通过移除载体将导电释放图案转印到绝缘体中; 在具有转印的导电消除图案的绝缘体的表面上形成包括与第二电路图案顺序堆叠的第三镀层和第二金属层的导电图案; 去除第一镀层和籽晶层; 并且去除第一和第二金属层可以提供具有高密度电路图案而不增加绝缘体量的电路板。

公开(公告)号：US08124880B2

公开(公告)日：2012-02-28

申请号：US11976207

申请日：2007-10-22

申请人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

发明人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC分类号： H05K1/03

CPC分类号： H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

摘要： A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator.

摘要翻译： 一种电路板的制造方法，其特征在于，包括：在堆叠在载体上的种子层上，形成导电消除图案，所述导电解像图案包括依次与第一电路图案对应地层叠的第一镀层，第一金属层和第二镀层 ; 将载体和绝缘体堆叠并压在一起，使得具有导电缓冲图案的载体的表面面向绝缘体; 通过移除载体将导电释放图案转印到绝缘体中; 在具有转印的导电消除图案的绝缘体的表面上形成包括与第二电路图案顺序堆叠的第三镀层和第二金属层的导电图案; 去除第一镀层和籽晶层; 并且去除第一和第二金属层可以提供具有高密度电路图案而不增加绝缘体量的电路板。

公开(公告)号：US08633392B2

公开(公告)日：2014-01-21

申请号：US13354438

申请日：2012-01-20

申请人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

发明人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC分类号： H05K1/02

CPC分类号： H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

摘要： A circuit board including: an insulator having a trench; a first circuit pattern formed to bury a portion of the trench; and a second circuit pattern formed on a surface of the insulator having the trench formed therein.

摘要翻译： 一种电路板，包括：具有沟槽的绝缘体; 形成为埋入沟槽的一部分的第一电路图案; 以及形成在其中形成有沟槽的绝缘体的表面上的第二电路图案。

公开(公告)号：US20080009128A1

公开(公告)日：2008-01-10

申请号：US11708339

申请日：2007-02-21

申请人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

发明人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC分类号： H01L21/44

CPC分类号： H05K3/205 ,  H05K3/4038 ,  H05K3/4617 ,  H05K2203/0733 ,  H05K2203/1572

摘要： A buried pattern substrate and a manufacturing method thereof are disclosed. A method of manufacturing a buried pattern substrate having a circuit pattern formed on a surface, in which the circuit pattern is connected electrically by a stud bump, includes (a) forming the circuit pattern and the stud bump by depositing a plating layer selectively on a seed layer of a carrier film, where the seed layer is laminated on a surface of the carrier film, (b) laminating and pressing the carrier film on an insulation layer such that the circuit pattern and the stud bump face the insulation layer, and (c) removing the carrier film and the seed layer, allows the circuit interconnection to be realized using a copper (Cu) stud bump, so that a drilling process for interconnection is unnecessary, the degree of freedom for circuit design is improved, a via land is made unnecessary and the size of a via is small, to allow higher density in a circuit.

摘要翻译： 公开了掩埋图案基板及其制造方法。 一种制造埋设图形衬底的方法，其中电路图案形成在电路图形通过柱形凸块电连接的表面上，包括：（a）通过在 晶种层层叠在载体膜的表面上的载体膜的种子层，（b）在绝缘层上层叠压制载体膜，使得电路图案和柱状凸块面向绝缘层，和 c）去除载体膜和种子层，允许使用铜（Cu）柱状凸块实现电路互连，使得不需要用于互连的钻孔工艺，提高了电路设计的自由度，通孔焊盘 不必要，并且通孔的尺寸小，以允许电路中的较高密度。

公开(公告)号：US20090242238A1

公开(公告)日：2009-10-01

申请号：US12457166

申请日：2009-06-02

申请人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

发明人： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC分类号： H05K1/09

CPC分类号： H05K3/205 ,  H05K3/4038 ,  H05K3/4617 ,  H05K2203/0733 ,  H05K2203/1572

摘要： A buried pattern substrate includes an insulation layer; a circuit pattern buried in the insulation layer such that a part thereof is exposed at a surface of the insulation layer; and a stud bump buried in the insulation layer such that one end portion is exposed at one surface of the insulation layer, and such that the other end portion is exposed at the other surface of the insulation layer.

摘要翻译： 掩埋图案衬底包括绝缘层; 埋置在绝缘层中的电路图案，使得其一部分在绝缘层的表面露出; 以及埋在所述绝缘层中的螺柱凸起，使得一个端部暴露在所述绝缘层的一个表面处，并且使得所述另一端部暴露在所述绝缘层的另一个表面处。

公开(公告)号：US20080098597A1

公开(公告)日：2008-05-01

申请号：US11976072

申请日：2007-10-19

申请人： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

发明人： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

IPC分类号： H05K3/02

CPC分类号： H05K3/20 ,  H05K3/0058 ,  H05K3/108 ,  H05K3/4611 ,  H05K3/4682 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2203/0152 ,  H05K2203/0376 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A method of manufacturing a circuit board is disclosed. A method of manufacturing a circuit board that includes forming a first circuit pattern on the insulation layer of a carrier, in which an insulation layer and a first seed layer are stacked in order; stacking and pressing the carrier and an insulation board with the side of the carrier having the first circuit pattern facing the insulation board; removing the carrier to transfer the first circuit pattern and the insulation layer onto the insulation board; and forming a second circuit pattern on the insulation layer transferred to the insulation board, allows fine pitch circuit patterns to enable the manufacture of fine circuit patterns of high density on the board, and allows the manufacture of a multi-layer circuit board with a simple process.

摘要翻译： 公开了一种制造电路板的方法。 一种制造电路板的方法，包括在载体的绝缘层上形成第一电路图案，其中绝缘层和第一种子层依次层叠; 堆叠并按压载体和绝缘板，其中载体侧具有面向绝缘板的第一电路图案; 移除载体以将第一电路图案和绝缘层转移到绝缘板上; 并且在转移到绝缘板的绝缘层上形成第二电路图案，允许精细的间距电路图案能够在板上制造高密度的精细电路图案，并且允许制造具有简单的多层电路板 处理。

公开(公告)号：US07992291B2

公开(公告)日：2011-08-09

申请号：US11976070

申请日：2007-10-19

申请人： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

发明人： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

IPC分类号： H05K3/20 ,  H05K1/18

CPC分类号： H05K3/205 ,  H01L21/4846 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K3/4007 ,  H05K2201/09745 ,  H05K2201/10674 ,  H05K2203/0338 ,  H05K2203/0435 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of manufacturing a circuit board, which includes a bump pad on which a solder bump may be placed, may include forming a solder pad on a surface of a first carrier; forming a metal film, which covers the solder pad and which extends to a bump pad forming region; forming a circuit layer and a circuit pattern, which are electrically connected with the metal film, on a surface of the first carrier; pressing the first carrier and an insulator such that a surface of the first carrier and the insulator faces each other; and removing the first carrier. Utilizing this method, the amount of solder for the contacting of a flip chip can be adjusted, and solder can be filled inside the board, so that after installing a chip, the overall thickness of the package can be reduced.

摘要翻译： 一种制造电路板的方法，包括可以放置焊锡凸块的凸块焊盘，可以包括在第一载体的表面上形成焊盘; 形成覆盖焊盘并延伸到凸块焊盘形成区域的金属膜; 在所述第一载体的表面上形成与所述金属膜电连接的电路层和电路图案; 按压所述第一载体和绝缘体，使得所述第一载体和所述绝缘体的表面彼此面对; 并移除第一载体。 利用这种方法，可以调节用于接合倒装芯片的焊料的量，并且可以在板内填充焊料，使得在安装芯片之后，可以减小封装的整体厚度。

公开(公告)号：US20080102410A1

公开(公告)日：2008-05-01

申请号：US11976211

申请日：2007-10-22

申请人： Ji-Eun Kim ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jong-Gyu Choi ,  Jeong-Woo Park ,  Sang-Duck Kim

发明人： Ji-Eun Kim ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jong-Gyu Choi ,  Jeong-Woo Park ,  Sang-Duck Kim

IPC分类号： G03C5/00

CPC分类号： H01L21/4857 ,  H01L23/13 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/183 ,  H05K3/108 ,  H05K3/20 ,  H05K3/4658 ,  H05K3/4697 ,  H05K2203/308 ,  H01L2224/0401

摘要： A method of manufacturing a printed circuit board is disclosed, in which a cavity is formed for embedding a component, which includes: providing a core board, in which an inner circuit is buried; forming a first via in the core board for interlayer conduction; selectively forming a first photoresist in a position on the core board in correspondence with a position of the cavity; stacking a first build-up layer, on which a first outer circuit is formed, on the core board; and selectively removing the first build-up layer in correspondence with the position of the cavity and removing the first photoresist. Utilizing the method, a board can be manufactured with greater precision, as the thickness tolerance of the cavity may be obtained by controlling the thickness of the photoresist, and the overall thickness of the board can be controlled by controlling the height of the cavity.

摘要翻译： 公开了一种制造印刷电路板的方法，其中形成用于嵌入部件的空腔，其包括：提供其中埋入内部电路的芯板; 在芯板中形成层间导电的第一通孔; 在所述芯板上与所述腔的位置对应地选择性地形成第一光致抗蚀剂; 在芯板上堆叠形成有第一外部电路的第一堆积层; 并且与空腔的位置相对应地选择性地去除第一堆积层并除去第一光致抗蚀剂。 利用该方法，可以通过控制光致抗蚀剂的厚度来获得更高精度的板，因为通过控制光致抗蚀剂的厚度可以获得空腔的厚度公差，并且可以通过控制空腔的高度来控制板的整体厚度。

公开(公告)号：US20110259627A1

公开(公告)日：2011-10-27

申请号：US13067883

申请日：2011-07-01

申请人： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

发明人： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

IPC分类号： H05K1/09 ,  H05K1/11

CPC分类号： H05K3/205 ,  H01L21/4846 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K3/4007 ,  H05K2201/09745 ,  H05K2201/10674 ,  H05K2203/0338 ,  H05K2203/0435 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A circuit board includes: an insulator having a groove; a circuit layer filling a portion of the groove; a solder pad on the circuit layer filling the remainder of the groove; and a circuit pattern electrically connected with the circuit layer, the circuit pattern buried in the insulator such that a portion of the circuit pattern is exposed at a surface of the insulator.

摘要翻译： 电路板包括：具有凹槽的绝缘体; 填充所述凹槽的一部分的电路层; 电路层上的填充凹槽其余部分的焊盘; 以及与电路层电连接的电路图案，电路图案埋在绝缘体中，使得电路图案的一部分在绝缘体的表面露出。