公开(公告)号：US06292066B1

公开(公告)日：2001-09-18

申请号：US09462564

申请日：2000-06-05

申请人： Shuji Shibuya ,  Hisato Takeuchi ,  Junichi Matsuura ,  Yuichi Tateyama ,  Takaharu Saeki

发明人： Shuji Shibuya ,  Hisato Takeuchi ,  Junichi Matsuura ,  Yuichi Tateyama ,  Takaharu Saeki

IPC分类号： H03L102

CPC分类号： G06G7/26 ,  H03B5/362 ,  H03B5/368 ,  H03B2201/0208 ,  H03L1/022 ,  H03L1/025 ,  H03L1/026 ,  H03L1/028

摘要： A temperature compensating crystal oscillation device includes a constant voltage circuit (12) for outputting a predetermined voltage independent of the ambient temperature, a temperature sensor circuit (13) for outputting a voltage in proportion to the ambient temperature, and a control circuit (14) for receiving the constant voltage output from the constant voltage circuit (12) and the voltage output in proportion to the temperature from the temperature sensor circuit (13) and for generating a control voltage (Vc) used for compensating a temperature characteristic of a quartz oscillator in the entire range of the ambient temperature through polygonal lines approximation of a negative cubic curve by using continuous lines. Furthermore, the crystal oscillation device includes a VCXO (15) whose oscillation frequency is controlled to be a predetermined value by the control voltage (Vc), and a ROM/RAM circuit (16) for storing temperature compensating parameters used for compensation of a temperature characteristic of the control voltage (Vc) for optimizing the oscillation frequency of the VCXO (15).

摘要翻译： 温度补偿晶体振荡装置包括用于输出与环境温度无关的预定电压的恒压电路（12），用于输出与环境温度成比例的电压的温度传感器电路（13），以及控制电路（14） 用于接收来自恒压电路（12）的恒定电压输出和与温度传感器电路（13）的温度成比例的电压输出，并产生用于补偿石英振荡器（13）的温度特性的控制电压（Vc） 在环境温度的整个范围内通过使用连续线的负三次曲线的折线近似。 此外，晶体振荡装置包括通过控制电压（Vc）将振荡频率控制为规定值的VCXO（15），以及用于存储用于补偿温度的温度补偿参数的ROM / RAM电路（16） 用于优化VCXO（15）的振荡频率的控制电压（Vc）的特性。

公开(公告)号：US5719533A

公开(公告)日：1998-02-17

申请号：US721291

申请日：1996-09-26

申请人： Shuji Shibuya ,  Hisato Takeuchi ,  Makoto Eguchi ,  Takaharu Saeki

发明人： Shuji Shibuya ,  Hisato Takeuchi ,  Makoto Eguchi ,  Takaharu Saeki

IPC分类号： H03L1/02 ,  H03B5/04 ,  H03B5/32 ,  H03K3/011

CPC分类号： H03L1/022

摘要： In order to realize highly accurate temperature compensation of a crystal oscillation frequency, a current in proportion to the cube of a difference between an ambient temperature T.sub.a and a reference temperature T.sub.0 is generated. For this purpose, provided are a first series circuit of two diodes; a second series circuit of three diodes; a third series circuit of two diodes; a fourth series circuit of three diodes; a current source for allowing a constant current to flow into the first series circuit; a current source for allowing a constant current to flow from the third series circuit; a current source for allowing a current in proportion to T.sub.a -T.sub.0 to flow into the second series circuit when T.sub.a .gtoreq.T.sub.0 and allowing a current in proportion to .vertline.T.sub.a -T.sub.0 .vertline. to flow from the fourth series circuit when T.sub.a

摘要翻译： 为了实现高精度的晶体振荡频率的温度补偿，产生与环境温度Ta和参考温度T0之间的差的立方成比例的电流。 为此，提供了两个二极管的第一串联电路; 三个二极管的第二个串联电路; 两个二极管的第三个串联电路; 三极二极管的第四个串联电路; 用于允许恒定电流流入第一串联电路的电流源; 用于允许恒定电流从第三串联电路流动的电流源; 当Ta> / = T0时允许与Ta-T0成比例的电流流入第二串联电路的电流源，并允许与| Ta-T0 |成比例的电流; 当Ta

公开(公告)号：US06197603B1

公开(公告)日：2001-03-06

申请号：US09157153

申请日：1998-09-18

申请人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

发明人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

IPC分类号： G01R3126

CPC分类号： G01R3/00 ,  G01R1/0735

摘要： Dispersion of a load may be kept within a predetermined allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane against a wafer by applying a pressure load to a plurality of places on a plane of the pressure members on the side opposite the wafer in a probe test step, burn-in test step which represent typical semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit at the same time.

摘要翻译： 即使当大量区域中的多个探针通过将设置在膜中的探针压在晶片上时，通过将压力负载施加到多个位置的平面上的多个位置，负载的分散也可以保持在预定容限内 在探针测试步骤中与晶片相对的一侧的压力构件，代表典型的半导体器件制造步骤的老化测试步骤。 因此，可以提供通过同时探测大量集成电路或大尺寸集成电路来提高半导体器件的可靠性和生产率的半导体器件及其制造方法。

公开(公告)号：US06455335B1

公开(公告)日：2002-09-24

申请号：US09653624

申请日：2000-08-31

申请人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

发明人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

IPC分类号： G01R3126

CPC分类号： G01R3/00 ,  G01R1/0735

摘要： Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.

公开(公告)号：US07198962B2

公开(公告)日：2007-04-03

申请号：US10411283

申请日：2003-04-11

申请人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

发明人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L21/00 ,  H01L21/48

CPC分类号： G01R3/00 ,  G01R1/0735

摘要： Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.

摘要翻译： 即使当大量区域中的多个探针通过将设置在膜中的探针压迫到晶片而将压力负载施加到压力构件的平面的多个位置时，负载的分散也可以保持在容许范围内 在作为半导体器件制造步骤之一的探针测试步骤/老化测试步骤中与晶片相对的一侧。 因此，可以提供通过同时探测大量集成电路或大尺寸集成电路来提高半导体器件的可靠性和生产率的半导体器件及其制造方法。

公开(公告)号：US06566150B2

公开(公告)日：2003-05-20

申请号：US10171695

申请日：2002-06-17

申请人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

发明人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

IPC分类号： G01R3126

CPC分类号： G01R3/00 ,  G01R1/0735

摘要： Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.