Pseudorandom binary sequence checker with control circuitry for end-of-test check
    1.
    发明授权
    Pseudorandom binary sequence checker with control circuitry for end-of-test check 有权
    具有用于测试结束检查的控制电路的伪随机二进制序列检查器

    公开(公告)号:US08413036B2

    公开(公告)日:2013-04-02

    申请号:US12324920

    申请日:2008-11-28

    CPC分类号: H04L1/244 G06F2217/14

    摘要: Control circuitry is coupled between an error event output and a data input of a pseudorandom binary sequence (PRBS) checker. The control circuitry is configured to switch between a first operating state in which a received PRBS signal is applied to the data input of the PRBS checker and a second operating state in which an error signal is applied to the data input of the PRBS checker, responsive to detection of a designated condition of the PRBS checker. In an illustrative embodiment, the designated condition is an end-of-test condition indicating that the PRBS checker has completed a test involving the received PRBS signal.

    摘要翻译: 控制电路耦合在错误事件输出和伪随机二进制序列(PRBS)检查器的数据输入之间。 控制电路被配置为在其中接收的PRBS信号被施加到PRBS检查器的数据输入的第一操作状态和其中错误信号被施加到PRBS检查器的数据输入的第二操作状态之间切换,响应 检测PRBS检查器的指定条件。 在说明性实施例中,指定条件是指示PRBS检查器已经完成涉及所接收的PRBS信号的测试的测试结束条件。

    Pseudorandom binary sequence checker with control circuitry for end-of-test check
    2.
    发明申请
    Pseudorandom binary sequence checker with control circuitry for end-of-test check 有权
    具有用于测试结束检查的控制电路的伪随机二进制序列检查器

    公开(公告)号:US20100138729A1

    公开(公告)日:2010-06-03

    申请号:US12324920

    申请日:2008-11-28

    IPC分类号: G06F11/07

    CPC分类号: H04L1/244 G06F2217/14

    摘要: Control circuitry is coupled between an error event output and a data input of a pseudorandom binary sequence (PRBS) checker. The control circuitry is configured to switch between a first operating state in which a received PRBS signal is applied to the data input of the PRBS checker and a second operating state in which an error signal is applied to the data input of the PRBS checker, responsive to detection of a designated condition of the PRBS checker. In an illustrative embodiment, the designated condition is an end-of-test condition indicating that the PRBS checker has completed a test involving the received PRBS signal.

    摘要翻译: 控制电路耦合在错误事件输出和伪随机二进制序列(PRBS)检查器的数据输入之间。 控制电路被配置为在其中接收的PRBS信号被施加到PRBS检查器的数据输入的第一操作状态和其中错误信号被施加到PRBS检查器的数据输入的第二操作状态之间切换,响应 检测PRBS检查器的指定条件。 在说明性实施例中,指定条件是指示PRBS检查器已经完成涉及所接收的PRBS信号的测试的测试结束条件。

    Delay Parameter Testing for Multiple-Device Master-slave Configuration Using a Single-Device Testing System
    3.
    发明申请
    Delay Parameter Testing for Multiple-Device Master-slave Configuration Using a Single-Device Testing System 审中-公开
    使用单设备测试系统进行多设备主从配置的延迟参数测试

    公开(公告)号:US20100262671A1

    公开(公告)日:2010-10-14

    申请号:US12423276

    申请日:2009-04-14

    IPC分类号: G06F15/16 G06F11/28

    摘要: Devices to be arranged in a master-slave configuration are individually tested using a testing system that ensures that the devices will satisfy an interconnection requirement of that configuration. The testing system configures a first device into one of a master mode of operation and a slave mode of operation, and adjusts frame starting positions of respective traffic flows associated with the configured mode until measured delay parameters of that mode substantially match corresponding ones of a selected set of prospective delay parameters. If the traffic flows of the one configured mode as adjusted are substantially error free, the first device is configured into the other mode, and frame starting positions of respective traffic flows associated with the other configured mode of the first device are adjusted until measured delay parameters of that mode substantially match corresponding ones of the selected set of prospective delay parameters. If the traffic flows of the other configured mode as adjusted are substantially error free, the first device is identified as satisfying the interconnection requirement.

    摘要翻译: 使用测试系统单独测试要配置在主从配置中的设备,以确保设备满足该配置的互连要求。 测试系统将第一设备配置为主操作模式和从属操作模式之一,并且调整与配置模式相关联的各个流量流的帧开始位置,直到该模式的测量延迟参数基本上与所选择的模式 一套预期延迟参数。 如果被调整的一个配置模式的业务流量基本上是无错误的,则将第一设备配置成另一模式,并且调整与第一设备的另一配置模式相关联的各个业务流的帧开始位置,直到测量的延迟参数 该模式基本上匹配所选择的一组预期延迟参数中的相应的一个。 如果调整后的其他配置模式的流量基本上是无误的,则将第一设备识别为满足互连要求。

    Framer/mapper/multiplexor device with 1+1 and equipment protection
    4.
    发明授权
    Framer/mapper/multiplexor device with 1+1 and equipment protection 有权
    1 + 1和设备保护的成帧器/映射器/多路复用器

    公开(公告)号:US07792132B2

    公开(公告)日:2010-09-07

    申请号:US12331807

    申请日:2008-12-10

    IPC分类号: H04L12/56

    CPC分类号: H04J3/1611 H04J3/14

    摘要: In one embodiment, the present invention is a framer/mapper/multiplexor (FMM) device that can simultaneously (i) send protection copies of both its working incoming high-speed (e.g., STS-12) signal and incoming low-speed signals to a protection FMM device, and (ii) receive corresponding protection signals from the protection FMM device. Furthermore, the FMM device can select between working and protection signals at a switching level (e.g., STS-1) lower than the high-speed level, allowing for 1+1 APS/MSP protection and equipment protection at the board level, the device level, and at the STS-1 level. Yet further, four or more FMM devices can be configured so that all FMM devices can communicate with their corresponding protection FMM devices using a single, shared, 4-pin link (e.g., quad-OC-3 mode), and still select between working and protection signals at the switching level (e.g., STS-1).

    摘要翻译: 在一个实施例中,本发明是一种成帧器/映射器/多路复用器(FMM)装置,其可以同时(i)将工作进入的高速(例如,STS-12)信号和进入的低速信号的保护副本发送到 保护FMM设备,以及(ii)从保护FMM设备接收相应的保护信号。 此外,FMM设备可以在低于高速电平的开关电平(例如,STS-1)之间选择工作和保护信号,从而允许在电路板级别进行1 + 1 APS / MSP保护和设备保护,设备 级别和STS-1级别。 此外,可以配置四个或更多个FMM设备,使得所有FMM设备可以使用单个共享的4引脚链路(例如,quad-OC-3模式)与其相应的保护FMM设备进行通信,并且仍然在工作之间进行选择 和开关电平的保护信号(例如,STS-1)。

    FRAMER/MAPPER/MULTIPLEXOR DEVICE WITH 1+1 AND EQUIPMENT PROTECTION
    5.
    发明申请
    FRAMER/MAPPER/MULTIPLEXOR DEVICE WITH 1+1 AND EQUIPMENT PROTECTION 有权
    具有1 + 1和设备保护的FRAMER / MAPPER / MULTIPLEXOR设备

    公开(公告)号:US20100142948A1

    公开(公告)日:2010-06-10

    申请号:US12331807

    申请日:2008-12-10

    IPC分类号: H04J14/00 H04L12/50

    CPC分类号: H04J3/1611 H04J3/14

    摘要: In one embodiment, the present invention is a framer/mapper/multiplexor (FMM) device that can simultaneously (i) send protection copies of both its working incoming high-speed (e.g., STS-12) signal and incoming low-speed signals to a protection FMM device, and (ii) receive corresponding protection signals from the protection FMM device. Furthermore, the FMM device can select between working and protection signals at a switching level (e.g., STS-1) lower than the high-speed level, allowing for 1+1 APS/MSP protection and equipment protection at the board level, the device level, and at the STS-1 level. Yet further, four or more FMM devices can be configured so that all FMM devices can communicate with their corresponding protection FMM devices using a single, shared, 4-pin link (e.g., quad-OC-3 mode), and still select between working and protection signals at the switching level (e.g., STS-1).

    摘要翻译: 在一个实施例中,本发明是一种成帧器/映射器/多路复用器(FMM)装置,其可以同时(i)将工作进入的高速(例如,STS-12)信号和进入的低速信号的保护副本发送到 保护FMM设备,以及(ii)从保护FMM设备接收相应的保护信号。 此外,FMM设备可以在低于高速电平的开关电平(例如,STS-1)之间选择工作和保护信号,从而允许在电路板级别进行1 + 1 APS / MSP保护和设备保护,设备 级别和STS-1级别。 此外,可以配置四个或更多个FMM设备,使得所有FMM设备可以使用单个共享的4引脚链路(例如,quad-OC-3模式)与其相应的保护FMM设备进行通信,并且仍然在工作之间进行选择 和开关电平的保护信号(例如,STS-1)。