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    DATA OUTPUT BUFFER AND MEMORY DEVICE
    1.
    发明申请
    DATA OUTPUT BUFFER AND MEMORY DEVICE 有权
    数据输出缓冲器和存储器件

    公开(公告)号：US20120099383A1

    公开(公告)日：2012-04-26

    申请号：US13239478

    申请日：2011-09-22

    申请人： Si-Hong Kim ,  Seung-Jun Bae ,  Jin-Il Lee ,  Kwang-Il Park

    发明人： Si-Hong Kim ,  Seung-Jun Bae ,  Jin-Il Lee ,  Kwang-Il Park

    IPC分类号： G11C7/00 ,  G11C7/10

    CPC分类号： G11C7/1057 ,  G11C29/022 ,  G11C29/028 ,  G11C2207/2254

    摘要： A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read data. The control unit adjusts a value of the termination impedance and a value of the drive impedance based on an output voltage at the external pin during a termination mode, and controls the driving unit to selectively perform one of the termination operation and the driving operation during a driving mode.

    摘要翻译： 数据输出缓冲器包括驱动单元和控制单元。 驱动单元选择性地执行向耦合到外部引脚的传输线提供终止阻抗的终止操作，以及在输出读取数据的同时向传输线提供驱动阻抗的驱动操作。 控制单元在终端模式期间根据外部引脚的输出电压来调整终端阻抗的值和驱动阻抗的值，并且控制驱动单元选择性地执行终止操作和驱动操作之一 驾驶模式。

    Data output buffer and memory device
    2.
    发明授权
    Data output buffer and memory device 有权
    数据输出缓冲器和存储器件

    公开(公告)号：US08553471B2

    公开(公告)日：2013-10-08

    申请号：US13239478

    申请日：2011-09-22

    申请人： Si-Hong Kim ,  Seung-Jun Bae ,  Jin-Il Lee ,  Kwang-Il Park

    发明人： Si-Hong Kim ,  Seung-Jun Bae ,  Jin-Il Lee ,  Kwang-Il Park

    IPC分类号： G11C7/10 ,  G11C7/00

    CPC分类号： G11C7/1057 ,  G11C29/022 ,  G11C29/028 ,  G11C2207/2254

    摘要： A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read data. The control unit adjusts a value of the termination impedance and a value of the drive impedance based on an output voltage at the external pin during a termination mode, and controls the driving unit to selectively perform one of the termination operation and the driving operation during a driving mode.

    摘要翻译： 数据输出缓冲器包括驱动单元和控制单元。 驱动单元选择性地执行向耦合到外部引脚的传输线提供终止阻抗的终止操作，以及在输出读取数据的同时向传输线提供驱动阻抗的驱动操作。 控制单元在终端模式期间根据外部引脚的输出电压来调整终端阻抗的值和驱动阻抗的值，并且控制驱动单元选择性地执行终止操作和驱动操作之一 驾驶模式。

    Semiconductor memory device and method of controlling the same
    5.
    发明授权
    Semiconductor memory device and method of controlling the same 有权
    半导体存储器件及其控制方法

    公开(公告)号：US08649238B2

    公开(公告)日：2014-02-11

    申请号：US13078218

    申请日：2011-04-01

    申请人： Dong-Min Kim ,  Young-Soo Sohn ,  Seung-Jun Bae ,  Kwang-Il Park

    发明人： Dong-Min Kim ,  Young-Soo Sohn ,  Seung-Jun Bae ,  Kwang-Il Park

    IPC分类号： G11C8/00

    CPC分类号： G11C8/12 ,  G11C8/18

    摘要： A semiconductor memory device includes a memory cell array, an address control unit and a logic circuit. The memory cell array includes a plurality of banks which are divided into a first bank block and a second bank block. The address control unit accesses the memory cell array. The logic circuit controls the address control unit based on a command and an address signal such that the first and second bank blocks commonly operate in a first operation mode, and the first and second bank blocks individually operate in a second operation mode.

    摘要翻译： 半导体存储器件包括存储单元阵列，地址控制单元和逻辑电路。 存储单元阵列包括被划分成第一存储块和第二存储块的多个存储体。 地址控制单元访问存储单元阵列。 逻辑电路基于命令和地址信号控制地址控制单元，使得第一和第二存储体块以第一操作模式共同操作，并且第一和第二存储体块以第二操作模式分别操作。

    Data write training method
    6.
    发明授权
    Data write training method 有权
    数据写入训练方法

    公开(公告)号：US08593901B2

    公开(公告)日：2013-11-26

    申请号：US13868425

    申请日：2013-04-23

    申请人： Tae-Young Oh ,  Young-Soo Sohn ,  Seung-Jun Bae ,  Kwang-Il Park

    发明人： Tae-Young Oh ,  Young-Soo Sohn ,  Seung-Jun Bae ,  Kwang-Il Park

    IPC分类号： G11C8/00

    CPC分类号： G11C7/22 ,  G11C7/1087 ,  G11C7/1093 ,  G11C2207/2254

    摘要： Embodiments may be directed to a method of operating a semiconductor device, the method including receiving a first write training command, receiving a first write data responsive to the first write training command through a first data line, and transmitting the first write data through a second data line. Transmitting the first write data is performed without an additional training command.

    摘要翻译： 实施例可以涉及一种操作半导体器件的方法，所述方法包括接收第一写入训练命令，响应于通过第一数据线的第一写入训练命令接收第一写入数据，以及通过第二数据线发送第一写入数据 数据线。 在不附加训练命令的情况下执行发送第一写入数据。

    High-speed phase-adjusted quadrature data rate (QDR) transceiver and method thereof
    7.
    发明授权
    High-speed phase-adjusted quadrature data rate (QDR) transceiver and method thereof 有权
    高速相位调整正交数据速率（QDR）收发器及其方法

    公开(公告)号：US07814359B2

    公开(公告)日：2010-10-12

    申请号：US11612800

    申请日：2006-12-19

    申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Sang-Woong Shin ,  Ho-Young Song

    发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Sang-Woong Shin ,  Ho-Young Song

    IPC分类号： G06F12/00

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

    摘要： A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver. In addition, since source synchronization is realized using a strobe signal, phase noise can be efficiently removed.

    摘要翻译： 提供了一种高速双倍或正交数据速率接口半导体器件及其方法。 用于高速数据传输的发射机（例如，数据传输半导体器件）发射第一选通信号和第二选通信号，第一选通信号和第二选通信号之间具有90度的相位差，第一组（字节）数据和 第二组（字节）数据。 发射机基于从接收机反馈的相位误差信息来调节第一和第二选通信号中的至少一个的相位，然后将相位调整的选通信号发送到接收机。 接收机从发送器接收第一和第二选通信号，并使用第一和第二选通信号接收数据的第一组（字节）和第二组（字节）数据。 接收机不需要锁相环（PLL）或延迟锁定环（DLL），从而减少接收机的电路面积和功耗。 此外，由于使用选通信号实现源同步，因此可以有效地去除相位噪声。

    Majority voter circuits and semiconductor devices including the same
    8.
    发明授权
    Majority voter circuits and semiconductor devices including the same 有权
    多数选民电路和半导体器件包括相同

    公开(公告)号：US07688102B2

    公开(公告)日：2010-03-30

    申请号：US11819600

    申请日：2007-06-28

    申请人： Seung-Jun Bae ,  Jeong-Don Lim ,  Gil-Shin Moon ,  Kwang-Il Park

    发明人： Seung-Jun Bae ,  Jeong-Don Lim ,  Gil-Shin Moon ,  Kwang-Il Park

    IPC分类号： H03K19/003

    CPC分类号： H03K19/23

    摘要： A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.

    摘要翻译： 多数选民电路被配置为基于第一输入数据和反相的第一输入数据生成选择信号。 第一输入数据和反相的第一输入数据都包括奇数位，奇数位包括第一类型的位和第二类型的位。 所生成的选择信号表示第一输入数据中的第一类型和第二类型的比特大多数。

    CIRCUIT AND METHODS FOR ELIMINATING SKEW BETWEEN SIGNALS IN SEMICODUCTOR INTEGRATED CIRCUIT
    9.
    发明申请
    CIRCUIT AND METHODS FOR ELIMINATING SKEW BETWEEN SIGNALS IN SEMICODUCTOR INTEGRATED CIRCUIT 审中-公开
    用于消除半导体集成电路中信号之间的差异的电路和方法

    公开(公告)号：US20090225622A1

    公开(公告)日：2009-09-10

    申请号：US12430163

    申请日：2009-04-27

    申请人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-Jin Jang

    发明人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-Jin Jang

    IPC分类号： G11C8/00

    CPC分类号： G11C7/22 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222

    摘要： A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.

    摘要翻译： 一种用于消除半导体存储器件和存储器控制器之间的接口中的数据与时钟信号之间的偏斜的电路，包括存储从半导体存储器件输出的边沿信息的边缘信息存储单元，伪数据模式生成单元，其输出伪 数据，包括与实际发送的数据类似的模式;相位检测单元，其从边缘信息存储单元接收边缘信息，并从伪数据模式产生单元接收伪数据，以检测数据和时钟信号之间的相位差，并产生 相应的检测结果，以及相位控制单元，其根据来自相位检测单元的相应检测结果控制时钟信号的相位，以便消除数据写入和读取操作中的每数据输入/输出引脚偏移 的半导体存储器件。