公开(公告)号：US20240232093A1

公开(公告)日：2024-07-11

申请号：US18094401

申请日：2023-01-09

Applicant: Silicon Motion, Inc.

Inventor： Jie-Hao Lee ,  Chien-Cheng Lin ,  Chang-Chieh Huang

IPC: G06F12/0873 ,  G06F12/02

CPC classification number: G06F12/0873 ,  G06F12/0253

Abstract: A method for performing data access management of a memory device in a predetermined communications architecture with aid of unbalanced table search and associated apparatus are provided. The method may include: utilizing a memory controller to receive a plurality of host commands from a host device through a transmission interface circuit of the memory controller, perform the unbalanced table search to receive a set of first data and a set of second data with first and second active blocks according to first and second commands among the host commands, respectively, and update first and second temporary physical-to-logical (P2L) address mapping tables; and selectively updating a first P2L address mapping table and a second P2L address mapping table according to the first temporary P2L address mapping table and the second temporary P2L address mapping table, respectively, for performing subsequent processing.

公开(公告)号：US09940058B2

公开(公告)日：2018-04-10

申请号：US15287998

申请日：2016-10-07

Applicant: Silicon Motion, Inc.

Inventor： Chien-Cheng Lin ,  Jie-Hao Lee

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/10 ,  G11C16/16 ,  G11C7/04 ,  G11C16/08 ,  G11C16/34 ,  G11C29/00

CPC classification number: G06F3/064 ,  G06F3/0616 ,  G06F3/0679 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/222 ,  G11C7/04 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3495 ,  G11C29/70 ,  G11C2211/5641

Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller distributes TLC-data blocks of the flash memory into three regions, obtains three sub-prewrite data sectors according to a prewrite data sector and a logic address, determines a first TLC-data block according to the logic address, selects a new first TLC-data block with the lowest erase count from the first region when the first TLC-data block has valid data, selects two TLC-data blocks according to the new first TLC-data block, writes the three sub-prewrite data sectors into the new first TLC-data block and the two selected TLC-data blocks, and maps the first new TLC-data block and the two selected TLC-data blocks to the logic address.

公开(公告)号：US09632880B2

公开(公告)日：2017-04-25

申请号：US14534488

申请日：2014-11-06

Applicant: Silicon Motion, Inc.

Inventor： Chien-Cheng Lin ,  Chia-Chi Liang ,  Chang-Chieh Huang ,  Jie-Hao Lee

IPC: G06F11/14 ,  G06F12/02 ,  G06F11/10 ,  G11C29/52 ,  G06F12/121 ,  G11C29/04

CPC classification number: G06F11/1469 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0679 ,  G06F11/1072 ,  G06F11/141 ,  G06F11/1435 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/121 ,  G06F2212/1032 ,  G06F2212/60 ,  G06F2212/69 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7209 ,  G11C11/56 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/5641 ,  Y02D10/13

Abstract: A data storage device with flash memory and a flash memory control method are disclosed, which upload the physical-to-logical address mapping information of one block to the flash memory section by section. A microcontroller is configured to allocate a flash memory to provide a first run-time write block. Between a first write operation and a second write operation of the first run-time write block, the microcontroller updates a logical-to-physical address mapping table in accordance with just part of a first physical-to-logical address mapping table. The logical-to-physical address mapping table is provided within the flash memory. The first physical-to-logical address mapping table is established in the random access memory to record logical addresses corresponding to physical addresses of one block.

公开(公告)号：US09606911B2

公开(公告)日：2017-03-28

申请号：US13942380

申请日：2013-07-15

Applicant: SILICON MOTION, INC.

Inventor： Chi-Lung Wang ,  Chia-Hsin Chen ,  Chien-Cheng Lin

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/10

CPC classification number: G06F12/0246 ,  G06F12/10 ,  G06F2212/7201

Abstract: A method for maintaining address mapping for a flash memory module is disclosed including: recording a first set of addresses corresponding to a first set of sequential logical addresses in a first section of a first addressing block; recording a second set of addresses corresponding to a second set of sequential logical addresses in a second section of the first addressing block; recording a third set of addresses corresponding to a third set of sequential logical addresses in a first section of a second addressing block; and recording a fourth set of addresses corresponding to a fourth set of sequential logical addresses in a second section of the second addressing block; wherein the second set of logical addresses is successive to the first set of logical addresses, and the third set of logical addresses is successive to the second set of logical addresses.

公开(公告)号：US20190213137A1

公开(公告)日：2019-07-11

申请号：US16022714

申请日：2018-06-29

Applicant: Silicon Motion Inc.

Inventor： Chien-Cheng Lin ,  Chia-Chi Liang ,  Jie-Hao Lee

IPC: G06F12/10

CPC classification number: G06F12/10 ,  G06F2212/1044 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: The present invention provides a method for managing a flash memory module, wherein the method comprises: reading a logical address to physical address (L2P) mapping table from the flash memory module; compressing the L2P mapping table to generate a compressed mapping table, wherein the compressed mapping table records a reference physical address and whether a corresponding physical address of each logical address is the reference physical address plus an offset value; and when receiving a read command asking for reading data corresponding to a specific logical address, referring to the compressed mapping table to determine a specific physical address corresponding to the specific logical address, and reading the data from the flash memory module according to the specific physical address.

公开(公告)号：US10168913B2

公开(公告)日：2019-01-01

申请号：US15618224

申请日：2017-06-09

Applicant: Silicon Motion, Inc.

Inventor： Chien-Cheng Lin ,  Jie-Hao Lee

IPC: G06F3/06 ,  G06F12/02

Abstract: The present invention provides a data storage device including a flash memory and a controller. The flash memory has a plurality of SLC-spare blocks, a plurality of TLC-data blocks and a plurality of TLC-spare blocks. The controller writes a first data sector into a first TLC-spare block, and determines whether a first TLC-data block corresponding to a first logical address has valid data. When the first TLC-data block has valid data, the controller performs a reverse-lookup to obtain a second logical address corresponding to the first TLC-data block, releases the first TLC-data block, a second TLC-data block and a third TLC-data block which are mapped to the second logical address, and maps the first TLC-spare block to the first logical address.

公开(公告)号：US09727271B2

公开(公告)日：2017-08-08

申请号：US15437543

申请日：2017-02-21

Applicant: Silicon Motion, Inc.

Inventor： Chien-Cheng Lin ,  Chia-Chi Liang ,  Chang-Chieh Huang ,  Jie-Hao Lee

IPC: G06F3/06 ,  G11C11/56 ,  G06F12/08 ,  G06F12/0802

CPC classification number: G06F11/1469 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0679 ,  G06F11/1072 ,  G06F11/141 ,  G06F11/1435 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/121 ,  G06F2212/1032 ,  G06F2212/60 ,  G06F2212/69 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7209 ,  G11C11/56 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/5641 ,  Y02D10/13

Abstract: A data storage device with flash memory and a flash memory control method are disclosed, in which the flash memory includes multi-level cells (MLCs) and single-level cells (SLCs). A microcontroller is configured to use the random access memory to cache data issued from the host before writing the data into the flash memory. The microcontroller is further configured to allocate the blocks of the flash memory to provide a first run-time write block containing multi-level cells and a second run-time write block containing single-level cells. Under control of the microcontroller, each physical page of data uploaded from the random access memory to the first run-time write block contains sequential data, and random data cached in the random access memory to form one physical page is written into the second run-time write block.

公开(公告)号：US09684568B2

公开(公告)日：2017-06-20

申请号：US14534633

申请日：2014-11-06

Applicant: Silicon Motion, Inc.

Inventor： Chien-Cheng Lin ,  Chia-Chi Liang ,  Chang-Chieh Huang ,  Jie-Hao Lee

IPC: G06F11/14 ,  G06F3/06 ,  G06F11/10 ,  G06F12/12 ,  G11C29/52 ,  G11C29/04 ,  G06F12/02 ,  G06F12/121

CPC classification number: G06F11/1469 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0679 ,  G06F11/1072 ,  G06F11/141 ,  G06F11/1435 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/121 ,  G06F2212/1032 ,  G06F2212/60 ,  G06F2212/69 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7209 ,  G11C11/56 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/5641 ,  Y02D10/13

Abstract: A data storage device and a flash memory control method with high erasing efficiency are disclosed. A microcontroller is configured to maintain a plurality of logical-to-physical address mapping tables and a link table on a flash memory to record mapping information between a host and the flash memory. The link table indicates positions of the plurality of logical-to-physical address mapping tables, and each entry in the link table corresponds to one logical-to-physical address mapping table. When erasing user data of logical addresses corresponding to N logical-to-physical address mapping tables, the microcontroller is configured to invalidate N entries corresponding to the N logical-to-physical address mapping tables in the link table, where N is an integer.

公开(公告)号：US09645894B2

公开(公告)日：2017-05-09

申请号：US14534535

申请日：2014-11-06

Applicant: Silicon Motion, Inc.

Inventor： Chien-Cheng Lin ,  Chia-Chi Liang ,  Chang-Chieh Huang ,  Jie-Hao Lee

IPC: G06F11/00 ,  G06F11/14 ,  G06F12/02 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G06F12/121 ,  G11C29/04

CPC classification number: G06F11/1469 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0679 ,  G06F11/1072 ,  G06F11/141 ,  G06F11/1435 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/121 ,  G06F2212/1032 ,  G06F2212/60 ,  G06F2212/69 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7209 ,  G11C11/56 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/5641 ,  Y02D10/13

Abstract: A data storage device and a flash memory control method with a power recovery design. A microcontroller is configured to allocate a flash memory to provide a first block from the blocks to work as a run-time write block for reception of write data. During a power recovery process due to an unexpected power-off event that interrupted write operations on the first block, the microcontroller is configured to allocate the flash memory to provide a second block from the blocks for complete data recovery of the first block and to replace the first block as the run-time write block.

公开(公告)号：US20240232074A1

公开(公告)日：2024-07-11

申请号：US18094402

申请日：2023-01-09

Applicant: Silicon Motion, Inc.

Inventor： Jie-Hao Lee ,  Chien-Cheng Lin ,  Chang-Chieh Huang

IPC: G06F12/02

CPC classification number: G06F12/0292 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2212/7201

Abstract: A method for performing data access management of a memory device in a predetermined communications architecture with aid of unbalanced table update and associated apparatus are provided. The method may include: utilizing a memory controller to receive a plurality of host commands from a host device through a transmission interface circuit of the memory controller, receive a set of first data and a set of second data with first and second active blocks according to first and second commands among the host commands, respectively, and update first and second temporary physical-to-logical (P2L) address mapping tables; and in response to a table region of any temporary P2L address mapping table being full, updating a first P2L address mapping table according to the first temporary P2L address mapping table and selectively updating a second P2L address mapping table according to the second temporary P2L address mapping table, for performing subsequent processing.