公开(公告)号：US20120221834A1

公开(公告)日：2012-08-30

申请号：US13219321

申请日：2011-08-26

申请人： Simon Knowles ,  Edward Andrews ,  Stephen Felix ,  Simon Huckett ,  Colman Hegarty ,  Fabienne Hegarty

发明人： Simon Knowles ,  Edward Andrews ,  Stephen Felix ,  Simon Huckett ,  Colman Hegarty ,  Fabienne Hegarty

IPC分类号： G06F15/76 ,  G06F9/06 ,  G06F9/30

CPC分类号： G06F9/30043 ,  G06F9/30163 ,  G06F9/30185 ,  G06F9/345 ,  G06F9/3889

摘要： A processor including: a first and at least a second data processing channel with enable logic for selectively enabling the second channel; logic for generating first and second storage addresses having a variable offset therebetween based on the same one or more address operands of the same storage access instruction; and circuitry for transferring data between the first address and a register of the first data processing channel and between the second address and a corresponding register of the second channel based on a same one or more register specifier operands of the access instruction. The first data processing channel performs an operation using one or more registers of the first data processing channel, and on condition of being enabled the second channel performs the same operation using a corresponding one or more of its own registers based on the same one or more operands of the data processing instruction.

摘要翻译： 一种处理器，包括：第一和至少第二数据处理通道，其具有用于选择性地启用第二通道的使能逻辑; 用于基于相同存储访问指令的相同一个或多个地址操作数产生具有可变偏移的第一和第二存储地址的逻辑; 以及用于基于访问指令的相同的一个或多个寄存器指定器操作数，在第一数据处理通道的第一地址和寄存器之间以及第二地址和第二通道的相应寄存器之间传送数据的电路。 第一数据处理通道使用第一数据处理通道的一个或多个寄存器来执行操作，并且在使能的条件下，第二通道使用相应的一个或多个基于相同的一个或多个寄存器的相应操作 数据处理指令的操作数。

公开(公告)号：US08782376B2

公开(公告)日：2014-07-15

申请号：US13219321

申请日：2011-08-26

申请人： Simon Knowles ,  Edward Andrews ,  Stephen Felix ,  Simon Huckett ,  Colman Hegarty

发明人： Simon Knowles ,  Edward Andrews ,  Stephen Felix ,  Simon Huckett ,  Colman Hegarty

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/30 ,  G06F9/345

CPC分类号： G06F9/30043 ,  G06F9/30163 ,  G06F9/30185 ,  G06F9/345 ,  G06F9/3889

摘要： A processor including: a first and at least a second data processing channel with enable logic for selectively enabling the second channel; logic for generating first and second storage addresses having a variable offset therebetween based on the same one or more address operands of the same storage access instruction; and circuitry for transferring data between the first address and a register of the first data processing channel and between the second address and a corresponding register of the second channel based on a same one or more register specifier operands of the access instruction. The first data processing channel performs an operation using one or more registers of the first data processing channel, and on condition of being enabled the second channel performs the same operation using a corresponding one or more of its own registers based on the same one or more operands of the data processing instruction.

摘要翻译： 一种处理器，包括：第一和至少第二数据处理通道，其具有用于选择性地启用第二通道的使能逻辑; 用于基于相同存储访问指令的相同一个或多个地址操作数产生具有可变偏移的第一和第二存储地址的逻辑; 以及用于基于访问指令的相同的一个或多个寄存器指定器操作数，在第一数据处理通道的第一地址和寄存器之间以及第二地址和第二通道的相应寄存器之间传送数据的电路。 第一数据处理通道使用第一数据处理通道的一个或多个寄存器来执行操作，并且在使能的条件下，第二通道使用相应的一个或多个基于相同的一个或多个寄存器的相应操作 数据处理指令的操作数。

公开(公告)号：US08509367B2

公开(公告)日：2013-08-13

申请号：US12330905

申请日：2008-12-09

申请人： Stephen Felix ,  Colman Hegarty

发明人： Stephen Felix ,  Colman Hegarty

IPC分类号： H04L7/00

CPC分类号： H04L7/0008

摘要： The invention provides a receiver comprising a data input and a strobe input. The strobe signal transitions whenever two consecutive bits in the data signal are the same. The receiver comprises combining means for generating a recovered clock signal from a combination of the data and strobe signals. The receiver also comprises a first sampling stage arranged to sample the data signal in dependence on the recovered clock signal, the first sampling stage comprising a plurality of sampling circuits and being arranged to obtain consecutive samples of the data signal using alternating ones of the sampling circuits. A second sampling stage is arranged to sample the data from the first sampling stage in dependence on a local system clock signal.

摘要翻译： 本发明提供一种接收机，包括数据输入和选通输入。 当数据信号中的两个连续位相同时，选通信号转换。 接收机包括用于从数据和选通信号的组合产生恢复的时钟信号的组合装置。 接收机还包括第一采样级，其被布置为根据恢复的时钟信号对数据信号进行采样，第一采样级包括多个采样电路，并且被布置为使用交替的采样电路来获得数据信号的连续采样 。 第二采样级被设置为根据本地系统时钟信号对来自第一采样级的数据进行采样。

公开(公告)号：US20090147888A1

公开(公告)日：2009-06-11

申请号：US12330905

申请日：2008-12-09

申请人： Stephen Felix ,  Colman Hegarty

发明人： Stephen Felix ,  Colman Hegarty

IPC分类号： H04L7/00 ,  H04L7/04 ,  H04L27/06

CPC分类号： H04L7/0008

摘要： The invention provides a receiver comprising a data input and a strobe input. The strobe signal transitions whenever two consecutive bits in the data signal are the same. The receiver comprises combining means for generating a recovered clock signal from a combination of the data and strobe signals. The receiver also comprises a first sampling stage arranged to sample the data signal in dependence on the recovered clock signal, the first sampling stage comprising a plurality of sampling circuits and being arranged to obtain consecutive samples of the data signal using alternating ones of the sampling circuits. A second sampling stage is arranged to sample the data from the first sampling stage in dependence on a local system clock signal.

摘要翻译： 本发明提供一种接收机，包括数据输入和选通输入。 当数据信号中的两个连续位相同时，选通信号转换。 接收机包括用于从数据和选通信号的组合产生恢复的时钟信号的组合装置。 接收机还包括第一采样级，其被布置为根据恢复的时钟信号对数据信号进行采样，第一采样级包括多个采样电路，并且被布置为使用交替的采样电路来获得数据信号的连续采样 。 第二采样级被设置为根据本地系统时钟信号对来自第一采样级的数据进行采样。

公开(公告)号：US07933405B2

公开(公告)日：2011-04-26

申请号：US11102266

申请日：2005-04-08

申请人： Simon Knowles ,  Stephen Felix

发明人： Simon Knowles ,  Stephen Felix

IPC分类号： H04L9/00

CPC分类号： G06F9/30032 ,  G06F9/30036 ,  G06F9/30043

摘要： According to embodiments of the invention, there is disclosed a data processing unit, a method of operating the same, computer program product and an instruction. In one embodiment according to the invention, there is provided a data processing unit for a computer processor, the data processing unit comprising a deep register access mechanism capable of performing a permutation operation on at least one data operand accessed from a register file of the computer processor, the permutation operation being performed in series with (i) register access for the data operand and (ii) execution of a data processing operation on the operand.

摘要翻译： 根据本发明的实施例，公开了一种数据处理单元，其操作方法，计算机程序产品和指令。 在根据本发明的一个实施例中，提供了一种用于计算机处理器的数据处理单元，该数据处理单元包括一个深度寄存器访问机制，能够对从计算机的寄存器文件访问的至少一个数据操作数执行置换操作 处理器，与（i）数据操作数的寄存器访问和（ii）对操作数的数据处理操作的执行串联执行的置换操作。

公开(公告)号：US20140143290A1

公开(公告)日：2014-05-22

申请号：US13638763

申请日：2011-04-07

申请人： Stephen Felix

发明人： Stephen Felix

IPC分类号： G06F7/523

CPC分类号： G06F7/523 ,  G06F7/53

摘要： A circuit for multiplying a digital signal by a variable gain, controlled in dependence on a digital gain control value. The circuit comprises: a multiplier input for receiving the digital signal; a multiplier output for outputting the digital signal multiplied by the gain; a plurality of multiplier stages each arranged to multiply by a respective predetermined multiplication factor; and switching circuitry arranged so as to apply selected ones of the multiplier stages in a multiplication path between the input and output, in dependence on the digital gain control value. The multiplication factors are arranged such that binary steps in the digital gain control value result in logarithmic steps in said gain.

摘要翻译： 用于将数字信号乘以可变增益的电路，其根据数字增益控制值进行控制。 该电路包括：用于接收数字信号的乘法器输入; 用于输出乘以增益的数字信号的乘法器输出; 多个乘法器级，每个乘法器级布置成乘以相应的预定乘法因子; 以及开关电路，其被布置为根据数字增益控制值在输入和输出之间的乘法路径中施加选择的乘法器级。 乘法因子被布置成使得数字增益控制值中的二进制步长导致所述增益中的对数步长。

公开(公告)号：US20120005471A1

公开(公告)日：2012-01-05

申请号：US13228170

申请日：2011-09-08

申请人： Peter Cumming ,  Stephen Felix

发明人： Peter Cumming ,  Stephen Felix

IPC分类号： G06F9/00

CPC分类号： G06F9/441

摘要： An integrated circuit is disclosed herein. In one embodiment, the integrated circuit includes: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties.

摘要翻译： 本文公开了集成电路。 在一个实施例中，集成电路包括：处理器; 可操作地耦合到所述处理器的多个外部引脚; 以及可操作地耦合到处理器的永久写入的存储器，所述存储器具有多个区域，每个区域存储用于引导处理器的一个或多个相应的引导属性。 处理器被编程为根据经由一个或多个外部引脚接收的指示来选择一个区域，以从所选择的区域检索一个或多个相应的引导属性，并使用一个或多个检索到的引导属性进行引导 。

公开(公告)号：US08024557B2

公开(公告)日：2011-09-20

申请号：US12127131

申请日：2008-05-27

申请人： Peter Cumming ,  Stephen Felix

发明人： Peter Cumming ,  Stephen Felix

IPC分类号： G06F9/00 ,  G06F9/24 ,  G06F15/177

CPC分类号： G06F9/441

摘要： An integrated circuit comprising: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties.

摘要翻译： 一种集成电路，包括：处理器; 可操作地耦合到所述处理器的多个外部引脚; 以及可操作地耦合到所述处理器的永久写入的存储器，所述存储器具有多个区域，每个区域存储用于引导所述处理器的一个或多个相应的引导属性。 处理器被编程为根据经由一个或多个外部引脚接收到的指示来选择一个区域，以从所选择的区域检索一个或多个相应的引导属性，并使用一个或多个检索到的引导属性进行引导 。

公开(公告)号：US07577048B2

公开(公告)日：2009-08-18

申请号：US11967540

申请日：2007-12-31

申请人： Stephen Felix

发明人： Stephen Felix

IPC分类号： G11C7/00

CPC分类号： G06F1/08 ,  G11C7/00

摘要： A double data rate memory interface circuit for transferring data between an interfacing device and double data rate memory device. The interface circuit comprises a data input for receiving a data signal from a first of those devices, and a strobe input for receiving a strobe signal from that first device. The interface circuit also comprises delay circuitry for supplying the data and strobe signals to the other device with a timing offset introduced therebetween. The delay circuitry comprises a software programmable storage medium and a digitally controllable delay element coupled to the storage medium, the delay element being arranged to control the timing offset in dependence on a delay setting programmed into that storage medium.

摘要翻译： 一种用于在接口设备和双数据速率存储设备之间传送数据的双数据速率存储器接口电路。 接口电路包括用于从这些设备中的第一个接收数据信号的数据输入和用于从该第一设备接收选通信号的选通输入。 接口电路还包括用于将数据和选通信号提供给另一个设备的延迟电路，其间引入定时偏移。 所述延迟电路包括软件可编程存储介质和耦合到所述存储介质的数字可控延迟元件，所述延迟元件被布置为根据编程到所述存储介质中的延迟设置来控制所述定时偏移。

公开(公告)号：US5646567A

公开(公告)日：1997-07-08

申请号：US518421

申请日：1995-08-24

申请人： Stephen Felix

发明人： Stephen Felix

IPC分类号： G01R31/28 ,  G01R31/30 ,  G01R31/3185 ,  G06F11/22 ,  H03K3/037 ,  H03K3/289 ,  H03K3/356

CPC分类号： H03K3/0375 ,  G01R31/318541 ,  G01R31/30

摘要： A scan cell is described which can function as either a positive edge triggered latch or a double edge triggered latch during normal functional operation of circuitry to be scan tested. It functions only as a positive edge triggered latch when scan testing of a logic structure is to be performed.

摘要翻译： 描述了在正被扫描测试的电路的正常功能操作期间可以起到正边沿触发锁存器或双边沿触发锁存器的扫描单元的作用。 当执行逻辑结构的扫描测试时，它仅用作正沿触发锁存器。