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公开(公告)号:US20050227499A1
公开(公告)日:2005-10-13
申请号:US10816606
申请日:2004-04-02
申请人: Sohyun Park , Wen Zhu , Tzu-Fang Huang , Li-Qun Xia , Hichem M'Saad
发明人: Sohyun Park , Wen Zhu , Tzu-Fang Huang , Li-Qun Xia , Hichem M'Saad
IPC分类号: C23C16/44 , H01L21/316 , H01L21/469 , H01L21/768
CPC分类号: H01L21/02126 , C23C16/4404 , H01L21/02211 , H01L21/02274 , H01L21/31633 , H01L21/76829 , Y10S438/913
摘要: A method for seasoning a chamber and depositing a low dielectric constant layer on a substrate in the chamber is provided. In one aspect, the method includes seasoning the chamber with a first mixture comprising one or more organosilicon compounds and one or more oxidizing gases and depositing a low dielectric constant layer on a substrate in the chamber from a second mixture comprising one or more organosilicon compounds and one or more oxidizing gases, wherein a ratio of the total flow rate of the organosilicon compounds to the total flow rate of the oxidizing gases in the first mixture is lower than the total flow rate of the organosilicon compounds to the total flow rate of the oxidizing gases in the second mixture.
摘要翻译: 提供了调节室的方法和在室中的基板上沉积低介电常数层。 在一个方面,所述方法包括用包含一种或多种有机硅化合物和一种或多种氧化性气体的第一混合物来调节室,并且从室内的衬底上沉积低介电常数层,所述第二混合物包含一种或多种有机硅化合物和 一种或多种氧化性气体,其中有机硅化合物的总流量与第一混合物中的氧化气体的总流量的比率低于有机硅化合物的总流量与氧化物的总流量的比率 第二混合物中的气体。
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公开(公告)号:US20060219175A1
公开(公告)日:2006-10-05
申请号:US11424723
申请日:2006-06-16
申请人: Sohyun Park , Wen Zhu , Tzu-Fang Huang , Li-Qun Xia , Hichem M'Saad
发明人: Sohyun Park , Wen Zhu , Tzu-Fang Huang , Li-Qun Xia , Hichem M'Saad
IPC分类号: C23C16/00
CPC分类号: H01L21/02126 , C23C16/4404 , H01L21/02211 , H01L21/02274 , H01L21/31633 , H01L21/76829 , Y10S438/913
摘要: A method for seasoning a chamber and depositing a low dielectric constant layer on a substrate in the chamber is provided. In one aspect, the method includes seasoning the chamber with a first mixture comprising one or more organosilicon compounds and one or more oxidizing gases and depositing a low dielectric constant layer on a substrate in the chamber from a second mixture comprising one or more organosilicon compounds and one or more oxidizing gases, wherein a ratio of the total flow rate of the organosilicon compounds to the total flow rate of the oxidizing gases in the first mixture is lower than the total flow rate of the organosilicon compounds to the total flow rate of the oxidizing gases in the second mixture.
摘要翻译: 提供了调节室的方法和在室中的基板上沉积低介电常数层。 在一个方面,所述方法包括用包含一种或多种有机硅化合物和一种或多种氧化性气体的第一混合物来调节室,并且从室内的衬底上沉积低介电常数层,所述第二混合物包含一种或多种有机硅化合物和 一种或多种氧化性气体,其中有机硅化合物的总流量与第一混合物中的氧化气体的总流量的比率低于有机硅化合物的总流量与氧化物的总流量的比率 第二混合物中的气体。
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公开(公告)号:US20060171653A1
公开(公告)日:2006-08-03
申请号:US11047785
申请日:2005-02-01
申请人: Alexandros Demos , Li-Qun Xia , Tzu-Fang Huang , Wen Zhu
发明人: Alexandros Demos , Li-Qun Xia , Tzu-Fang Huang , Wen Zhu
IPC分类号: G02B6/00
CPC分类号: H01L21/3105 , H01L21/02126 , H01L21/02271 , H01L21/02351 , H01L21/31633 , H01L21/76825
摘要: According to one embodiment of the invention, a method of modifying a mechanical, physical and/or electrical property of a dielectric layer comprises exposing the dielectric layer to a first dose of electron beam radiation at a first energy level; and thereafter, exposing the dielectric layer to a second dose of electron beam radiation at a second energy level that is different from the first energy level.
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公开(公告)号:US07435685B2
公开(公告)日:2008-10-14
申请号:US11531493
申请日:2006-09-13
申请人: Gerardo A. Delgadino , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li Huang , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
发明人: Gerardo A. Delgadino , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li Huang , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
IPC分类号: H01L21/311
CPC分类号: H01L21/76826 , H01L21/76811 , H01L21/76813
摘要: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.
摘要翻译: 一种制造互连结构的方法,包括将通孔蚀刻到上部低K电介质层中并进入下部低K电介质层的硬化部分。 通孔由形成在光致抗蚀剂层中的图案限定。 然后剥离光致抗蚀剂层,并且将由硬掩模限定的通孔的沟槽蚀刻到上部低K电介质层中,并且同时蚀刻到下部低K电介质层的硬化部分中的通孔为 进一步蚀刻到下部低K介电层中。 结果是低K电介质双镶嵌结构。
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5.
公开(公告)号:US20080145998A1
公开(公告)日:2008-06-19
申请号:US11531493
申请日:2006-09-13
申请人: GERARDO A. DELGADINO , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li Huang , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
发明人: GERARDO A. DELGADINO , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li Huang , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
IPC分类号: H01L21/76
CPC分类号: H01L21/76826 , H01L21/76811 , H01L21/76813
摘要: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.
摘要翻译: 一种制造互连结构的方法,包括将通孔蚀刻到上部低K电介质层中并进入下部低K电介质层的硬化部分。 通孔由形成在光致抗蚀剂层中的图案限定。 然后剥离光致抗蚀剂层,并且将由硬掩模限定的通孔的沟槽蚀刻到上部低K电介质层中,并且同时蚀刻到下部低K电介质层的硬化部分中的通孔是 进一步蚀刻到下部低K介电层中。 结果是低K电介质双镶嵌结构。
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公开(公告)号:US07132369B2
公开(公告)日:2006-11-07
申请号:US10745344
申请日:2003-12-22
申请人: Gerardo A. Delgadino , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
发明人: Gerardo A. Delgadino , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
IPC分类号: H01L21/302
CPC分类号: H01L21/76826 , H01L21/76811 , H01L21/76813
摘要: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.
摘要翻译: 一种制造互连结构的方法,包括将通孔蚀刻到上部低K电介质层中并进入下部低K电介质层的硬化部分。 通孔由形成在光致抗蚀剂层中的图案限定。 然后剥离光致抗蚀剂层,并且将由硬掩模限定的通孔的沟槽蚀刻到上部低K电介质层中,并且同时蚀刻到下部低K电介质层的硬化部分中的通孔为 进一步蚀刻到下部低K介电层中。 结果是低K电介质双镶嵌结构。
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公开(公告)号:US08354870B2
公开(公告)日:2013-01-15
申请号:US12828460
申请日:2010-07-01
申请人: Hao Qiong Chen , Wen Zhu
发明人: Hao Qiong Chen , Wen Zhu
IPC分类号: H03K3/00
CPC分类号: G06F1/324 , G06F1/08 , G06F1/10 , Y02D10/126
摘要: A clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the one of the inputs to provide on the output, the switch including elements that, prevent the providing of a truncated version of any of the clock sources on the output, always provide a clock signal on the output, and always maintain phase alignment and pulse ratio of the clock sources on the output.
摘要翻译: 一种时钟切换电路,具有用于接收至少两个不同时钟源的至少两个输入端,用于提供所选择的一个时钟源的输出端以及用于选择输入中的一个以提供输出的开关,该开关包括 阻止在输出上提供任何时钟源的截断版本的元件总是在输出端提供时钟信号,并且始终保持输出端上时钟源的相位对准和脉冲比。
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公开(公告)号:US07102861B2
公开(公告)日:2006-09-05
申请号:US10748437
申请日:2003-12-31
申请人: Julian Cave , André Hamel , Vijay Sood , Dan Watson , Wen Zhu
发明人: Julian Cave , André Hamel , Vijay Sood , Dan Watson , Wen Zhu
摘要: A cryogenic current limiting fuse is disclosed together with a method of manufacturing a cryogenic current limiting fuse, the cryogenic current limiting fuse comprising a first cryogenic composite and a second cryogenic composite wherein at least one of the first and the second cryogenic composites has a non-linear and increasing resistivity with respect to at least one of temperature and current.
摘要翻译: 公开了一种低温限流熔断器以及制造低温限流熔断器的方法,该低温限流熔断器包括第一低温复合材料和第二低温复合材料,其中第一和第二低温复合材料中的至少一个具有非限制性熔融物, 相对于温度和电流中的至少一个的线性和增加的电阻率。
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公开(公告)号:US08365243B1
公开(公告)日:2013-01-29
申请号:US12835763
申请日:2010-07-14
申请人: Minggang Lu , Pei Zhang , Jing Li , Wen Zhu
发明人: Minggang Lu , Pei Zhang , Jing Li , Wen Zhu
IPC分类号: G06F21/00
CPC分类号: G06F21/6209 , G06F21/10 , G06F2221/2111
摘要: Prevention of sensitive images such as photographs and video clips from being leaked from an organization uses geo-tagging metadata. A mobile computing device includes a software agent that implements a data loss prevention policy and a database of sensitive geographic areas defined by latitude and longitude coordinates. When an image is attempted to be stored on the device (or sent, received, renamed, copied, etc.) a software hook module detects the operation and obtains the geo-tagging metadata from the image for the agent. The agent compares the metadata of the image with each sensitive area found in its database to determine if the image was taken at a location within a sensitive area. If not, the operation is allowed, if so, the operation may be blocked, restricted or a warning may be sent to the user of the device or to another computer within the organization.
摘要翻译: 防止从组织泄漏的敏感图像(如照片和视频剪辑)使用地理标记元数据。 移动计算设备包括实现数据丢失预防策略的软件代理和由纬度和经度坐标定义的敏感地理区域的数据库。 当尝试将图像存储在设备上(或发送,接收,重命名,复制等)时,软件挂钩模块检测操作,并从代理的图像中获取地理标记元数据。 代理将图像的元数据与其数据库中找到的每个敏感区域进行比较,以确定图像是否在敏感区域内的某个位置拍摄。 如果没有,则允许操作,如果是,可能会阻止,限制操作或向设备的用户或组织内的其他计算机发送警告。
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公开(公告)号:US20060018346A1
公开(公告)日:2006-01-26
申请号:US10895764
申请日:2004-07-21
申请人: Wen Zhu
发明人: Wen Zhu
IPC分类号: H04J3/06
CPC分类号: H04J3/14 , H04J3/1623
摘要: A method and apparatus for detecting the C-bit parity application of DS3 makes use of the relative state of the CP-bits and the P-bits in one or more M-frames alone or in combination with the state of the AIC signal. In one implementation, the invention is a detector circuit that is adapted to receive a CP-bit and a P-bit from each of a group of one or more M-frames of a DS3 service. For each M-frame in the group, the detector circuit performs a logical XOR between the CP-bit and the P-bit for that M-frame. The detector circuit further performs a logical OR between the XOR results from each M-frame in the group and outputs a C-bit parity format detect signal if the result is zero.
摘要翻译: 用于检测DS3的C位奇偶校验应用的方法和装置使得单独的一个或多个M帧中的CP比特和P比特的相对状态或与AIC信号的状态相结合。 在一个实现中,本发明是一种检测器电路,其适于从DS3服务的一个或多个M帧的组中的每一个接收CP位和P位。 对于组中的每个M帧,检测器电路在该CP位和该M帧的P位之间执行逻辑异或。 检测器电路还在组中的每个M帧的XOR结果之间执行逻辑或运算,如果结果为零,则输出C位奇偶校验格式检测信号。
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