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    SUSPENDED GERMANIUM PHOTODETECTOR FOR SILICON WAVEGUIDE
    1.
    发明申请
    SUSPENDED GERMANIUM PHOTODETECTOR FOR SILICON WAVEGUIDE 有权
    用于硅波长的停止的德国光电转换器

    公开(公告)号：US20110143482A1

    公开(公告)日：2011-06-16

    申请号：US13005821

    申请日：2011-01-13

    申请人： Solomon Assefa ,  Jack O. Chu ,  Martin M. Frank ,  William M. Green ,  Young-hee Kim ,  George G. Totir ,  Joris Van Campenhout ,  Yurri A. Vlasov ,  Ying Zhang

    发明人： Solomon Assefa ,  Jack O. Chu ,  Martin M. Frank ,  William M. Green ,  Young-hee Kim ,  George G. Totir ,  Joris Van Campenhout ,  Yurri A. Vlasov ,  Ying Zhang

    IPC分类号： H01L31/18

    CPC分类号： H01L31/1804 ,  B82Y20/00 ,  G02B6/12004 ,  G02B6/136 ,  G02B2006/12123 ,  H01L31/109 ,  H01L31/1812 ,  Y02E10/547 ,  Y02P70/521

    摘要： A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.

    摘要翻译： 在第一外延硅层的顶表面上外延地形成第一硅锗合金层，第二外延硅层，第二硅锗层和锗层的垂直叠层。 第二外延硅层，第二硅锗层和锗层通过介电盖部分，电介质间隔物和第一硅锗层被图案化和封装。 在第一和第二硅层之间去除硅锗层以形成硅锗台面结构，其结构上支撑包括硅部分，硅锗合金部分，锗光电检测器和介电帽部分的叠层的悬垂结构。 锗光电探测器由硅锗台面结构悬挂而不邻接硅波导。 锗扩散到硅波导和锗检测器中的缺陷密度被最小化。

    Suspended germanium photodetector for silicon waveguide
    2.
    发明授权
    Suspended germanium photodetector for silicon waveguide 有权
    用于硅波导的悬浮锗光电探测器

    公开(公告)号：US08178382B2

    公开(公告)日：2012-05-15

    申请号：US13005821

    申请日：2011-01-13

    申请人： Solomon Assefa ,  Jack O. Chu ,  Martin M. Frank ,  William M. Green ,  Young-hee Kim ,  George G. Totir ,  Joris Van Campenhout ,  Yurri A. Vlasov ,  Ying Zhang

    发明人： Solomon Assefa ,  Jack O. Chu ,  Martin M. Frank ,  William M. Green ,  Young-hee Kim ,  George G. Totir ,  Joris Van Campenhout ,  Yurri A. Vlasov ,  Ying Zhang

    IPC分类号： H01L31/18

    CPC分类号： H01L31/1804 ,  B82Y20/00 ,  G02B6/12004 ,  G02B6/136 ,  G02B2006/12123 ,  H01L31/109 ,  H01L31/1812 ,  Y02E10/547 ,  Y02P70/521

    摘要： A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.

    摘要翻译： 在第一外延硅层的顶表面上外延地形成第一硅锗合金层，第二外延硅层，第二硅锗层和锗层的垂直叠层。 第二外延硅层，第二硅锗层和锗层通过介电盖部分，电介质间隔物和第一硅锗层被图案化和封装。 在第一和第二硅层之间去除硅锗层以形成硅锗台面结构，其结构上支撑包括硅部分，硅锗合金部分，锗光电检测器和介电帽部分的叠层的悬垂结构。 锗光电探测器由硅锗台面结构悬挂而不邻接硅波导。 锗扩散到硅波导和锗检测器中的缺陷密度被最小化。

    Suspended germanium photodetector for silicon waveguide
    3.
    发明授权
    Suspended germanium photodetector for silicon waveguide 有权
    用于硅波导的悬浮锗光电探测器

    公开(公告)号：US07902620B2

    公开(公告)日：2011-03-08

    申请号：US12191687

    申请日：2008-08-14

    申请人： Solomon Assefa ,  Jack O. Chu ,  Martin M. Frank ,  William M. Green ,  Young-hee Kim ,  George G. Totir ,  Joris Van Campenhout ,  Yurii A. Vlasov ,  Ying Zhang

    发明人： Solomon Assefa ,  Jack O. Chu ,  Martin M. Frank ,  William M. Green ,  Young-hee Kim ,  George G. Totir ,  Joris Van Campenhout ,  Yurii A. Vlasov ,  Ying Zhang

    IPC分类号： H01L31/18

    CPC分类号： H01L31/1804 ,  B82Y20/00 ,  G02B6/12004 ,  G02B6/136 ,  G02B2006/12123 ,  H01L31/109 ,  H01L31/1812 ,  Y02E10/547 ,  Y02P70/521

    摘要： A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.

    摘要翻译： 在第一外延硅层的顶表面上外延地形成第一硅锗合金层，第二外延硅层，第二硅锗层和锗层的垂直叠层。 第二外延硅层，第二硅锗层和锗层通过介电盖部分，电介质间隔物和第一硅锗层被图案化和封装。 在第一和第二硅层之间移除硅锗层以形成硅锗台面结构，其结构上支撑包括硅部分，硅锗合金部分，锗光电检测器和介电帽部分的叠层的悬垂结构。 锗光电探测器由硅锗台面结构悬挂而不邻接硅波导。 锗扩散到硅波导和锗检测器中的缺陷密度被最小化。

    CMOS integration scheme employing a silicide electrode and a silicide-germanide alloy electrode
    5.
    发明授权
    CMOS integration scheme employing a silicide electrode and a silicide-germanide alloy electrode 失效
    CMOS集成方案采用硅化物电极和硅化锗 - 锗化物合金电极

    公开(公告)号：US07749847B2

    公开(公告)日：2010-07-06

    申请号：US12031224

    申请日：2008-02-14

    申请人： Cyril Cabral, Jr. ,  Jack O. Chu ,  Young-Hee Kim

    发明人： Cyril Cabral, Jr. ,  Jack O. Chu ,  Young-Hee Kim

    IPC分类号： H01L21/8238 ,  H01L27/092

    CPC分类号： H01L21/823835 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4933 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  Y10S438/933

    摘要： A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) are formed by patterning of a gate dielectric layer, a thin silicon layer, and a silicon-germanium alloy layer. After formation of the source/drain regions and gate spacers, silicon germanium alloy portions are removed from gate stacks. A dielectric layer is formed and patterned to cover an NFET gate electrode, while exposing a thin silicon portion for a PFET. Germanium is selectively deposited on semiconductor surfaces including the exposed silicon portion. The dielectric layer is removed and a metal layer is deposited and reacted with underlying semiconductor material to form a metal silicide for a gate electrode of the NFET, while forming a metal silicide-germanide alloy for a gate electrode of the PFET.

    摘要翻译： 通过构图栅极电介质层，薄硅层和硅 - 锗合金层来形成p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。 在形成源极/漏极区域和栅极间隔物之后，从栅极叠层去除硅锗合金部分。 形成介电层并图案化以覆盖NFET栅电极，同时暴露用于PFET的薄硅部分。 锗选择性地沉积在包括暴露的硅部分的半导体表面上。 去除电介质层，并沉积金属层并与下面的半导体材料反应以形成用于NFET的栅电极的金属硅化物，同时形成用于PFET的栅电极的金属硅化物 - 锗化物合金。

    CMOS INTEGRATION SCHEME EMPLOYING A SILICIDE ELECTRODE AND A SILICIDE-GERMANIDE ALLOY ELECTRODE
    6.
    发明申请
    CMOS INTEGRATION SCHEME EMPLOYING A SILICIDE ELECTRODE AND A SILICIDE-GERMANIDE ALLOY ELECTRODE 失效
    使用硅酮电极和硅锗合金电极的CMOS集成方案

    公开(公告)号：US20090206413A1

    公开(公告)日：2009-08-20

    申请号：US12031224

    申请日：2008-02-14

    申请人： Cyril Cabral, JR. ,  Jack O. Chu ,  Young-Hee Kim

    发明人： Cyril Cabral, JR. ,  Jack O. Chu ,  Young-Hee Kim

    IPC分类号： H01L21/8238 ,  H01L27/092

    CPC分类号： H01L21/823835 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4933 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  Y10S438/933

    摘要： A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) are formed by patterning of a gate dielectric layer, a thin silicon layer, and a silicon-germanium alloy layer. After formation of the source/drain regions and gate spacers, silicon germanium alloy portions are removed from gate stacks. A dielectric layer is formed and patterned to cover an NFET gate electrode, while exposing a thin silicon portion for a PFET. Germanium is selectively deposited on semiconductor surfaces including the exposed silicon portion. The dielectric layer is removed and a metal layer is deposited and reacted with underlying semiconductor material to form a metal silicide for a gate electrode of the NFET, while forming a metal silicide-germanide alloy for a gate electrode of the PFET.

    摘要翻译： 通过构图栅极电介质层，薄硅层和硅 - 锗合金层来形成p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。 在形成源极/漏极区域和栅极间隔物之后，从栅极叠层去除硅锗合金部分。 形成介电层并图案化以覆盖NFET栅电极，同时暴露用于PFET的薄硅部分。 锗选择性地沉积在包括暴露的硅部分的半导体表面上。 去除电介质层，并沉积金属层并与下面的半导体材料反应以形成用于NFET的栅电极的金属硅化物，同时形成用于PFET的栅电极的金属硅化物 - 锗化物合金。

    BEOL compatible FET structrure
    7.
    发明授权
    BEOL compatible FET structrure 有权
    BEOL兼容FET结构

    公开(公告)号：US08569803B2

    公开(公告)日：2013-10-29

    申请号：US13572742

    申请日：2012-08-13

    申请人： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

    发明人： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

    IPC分类号： H01L29/76

    CPC分类号： H01L23/5226 ,  H01L23/53271 ,  H01L27/124 ,  H01L27/1248 ,  H01L2924/0002 ,  H01L2924/00

    摘要： This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

    摘要翻译： 本发明提供了用于在线路后端（BEOL）互连结构中并入薄膜晶体管的结构和制造工艺。 所描述的结构和制造工艺与BEOL互连结构的处理要求相兼容。 结构和制造工艺利用已经并入到互连布线层中的现有处理步骤和材料，以便降低与在这些层级中引入薄膜晶体管相关联的附加成本。 与现有技术的3D集成方法相比，该结构能够实现多层次的垂直（3D）集成，具有改进的可制造性和可靠性。

    Formation of a graphene layer on a large substrate
    8.
    发明授权
    Formation of a graphene layer on a large substrate 有权
    在大基体上形成石墨烯层

    公开(公告)号：US08541769B2

    公开(公告)日：2013-09-24

    申请号：US12942490

    申请日：2010-11-09

    申请人： Jack O. Chu ,  Christos D. Dimitrakopoulos ,  Marcus O. Freitag ,  Alfred Grill ,  Timothy J. McArdle ,  Robert L. Wisnieff

    发明人： Jack O. Chu ,  Christos D. Dimitrakopoulos ,  Marcus O. Freitag ,  Alfred Grill ,  Timothy J. McArdle ,  Robert L. Wisnieff

    IPC分类号： H01L29/12

    CPC分类号： H01L21/02447 ,  H01L21/02378 ,  H01L21/0242 ,  H01L21/02527 ,  H01L21/02612 ,  H01L21/0262 ,  H01L21/02656 ,  H01L29/1606 ,  H01L29/267

    摘要： A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.

    摘要翻译： 单晶碳化硅层可以在单晶蓝宝石衬底上生长。 随后，在超高真空环境中的高温退火期间，可以通过转换单晶硅层的表面层来形成石墨烯层。 或者，石墨烯层可以沉积在单晶碳化硅层的暴露表面上。 石墨烯层也可以直接形成在蓝宝石衬底的表面上或直接在碳化硅衬底的表面上形成。 另外，也可以在半导体基板上的碳化​​硅层上形成石墨烯层。 直径为6英寸或更大的蓝宝石衬底和半导体衬底的商业可用性允许在商业可扩展的衬底上形成石墨烯层，用于使用石墨烯层的器件的低成本制造。

    GRAPHENE GROWTH ON A CARBON-CONTAINING SEMICONDUCTOR LAYER
    9.
    发明申请
    GRAPHENE GROWTH ON A CARBON-CONTAINING SEMICONDUCTOR LAYER 有权
    含碳的半导体层的石墨生长

    公开(公告)号：US20120193603A1

    公开(公告)日：2012-08-02

    申请号：US13443003

    申请日：2012-04-10

    申请人： Jack O. Chu ,  Christos D. Dimitrakopoulos ,  Alfred Grill ,  Chun-yung Sung

    发明人： Jack O. Chu ,  Christos D. Dimitrakopoulos ,  Alfred Grill ,  Chun-yung Sung

    IPC分类号： H01L29/24

    CPC分类号： H01L29/1606 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/184 ,  C01B2204/04 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/02667 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/161 ,  Y10T428/265

    摘要： A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm.

    摘要翻译： 半导体 - 碳合金层形成在半导体衬底的表面上，半导体衬底的表面可以是诸如硅衬底的市售半导体衬底。 半导体 - 碳合金层在高温退火期间被转化为至少一个石墨烯层，在此期间半导体 - 碳合金层表面上的半导体材料对碳原子有选择性的蒸发。 随着半导体原子被选择性地去除并且半导体 - 碳合金层的表面上的碳浓度增加，半导体 - 碳合金层顶层中剩余的碳原子聚结形成具有至少一个石墨烯单层的石墨烯层 。 因此，可以在直径为200mm或300mm的市售半导体衬底上提供石墨烯层。