公开(公告)号：US20100038788A1

公开(公告)日：2010-02-18

申请号：US12607267

申请日：2009-10-28

申请人： Jeong Tae KIM ,  Baek Mann KIM ,  Soo Hyun KIM ,  Young Jin LEE ,  Dong Ha JUNG

发明人： Jeong Tae KIM ,  Baek Mann KIM ,  Soo Hyun KIM ,  Young Jin LEE ,  Dong Ha JUNG

IPC分类号： H01L23/532

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76856 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-layered metal line of a semiconductor device includes a semiconductor substrate; a lower metal line formed on the semiconductor substrate and recessed on a surface thereof; an insulation layer formed on the semiconductor substrate including the lower metal line and having a damascene pattern for exposing a recessed portion of the lower metal line and for delimiting an upper metal line forming region; a glue layer formed on a surface of the recessed portion of the lower metal line; a first diffusion barrier formed on the glue layer to fill the recessed portion of the lower metal line; a second diffusion barrier formed on the glue layer and the first diffusion barrier; a third diffusion barrier formed on the second diffusion barrier and a surface of the damascene pattern; and an upper metal line formed on the third diffusion barrier to fill the damascene pattern.

摘要翻译： 半导体器件的多层金属线包括半导体衬底; 形成在半导体衬底上并在其表面上凹陷的下金属线; 形成在所述半导体衬底上的绝缘层，所述绝缘层包括所述下金属线并且具有用于暴露所述下金属线的凹陷部分并限定上金属线形成区域的镶嵌图案; 形成在下金属线的凹部的表面上的胶层; 形成在所述胶层上以填充所述下金属线的凹部的第一扩散阻挡层; 形成在所述胶层和所述第一扩散阻挡层上的第二扩散阻挡层; 形成在所述第二扩散阻挡层上的第三扩散阻挡层和所述镶嵌图案的表面; 以及形成在第三扩散阻挡层上以填充镶嵌图案的上金属线。

公开(公告)号：US20080157370A1

公开(公告)日：2008-07-03

申请号：US11756005

申请日：2007-05-31

申请人： Dong Ha JUNG ,  Baek Mann KIM ,  Soo Hyun KIM ,  Young Jin LEE ,  Sun Woo HWANG ,  Jeong Tae KIM

发明人： Dong Ha JUNG ,  Baek Mann KIM ,  Soo Hyun KIM ,  Young Jin LEE ,  Sun Woo HWANG ,  Jeong Tae KIM

IPC分类号： H01L23/52 ,  H01L21/3205

CPC分类号： H01L21/76879 ,  H01L21/76831 ,  H01L21/76856 ,  H01L21/76886 ,  H01L21/76888 ,  H01L23/53223 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO2 layer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuO2 layer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.

摘要翻译： 半导体器件的金属布线包括半导体衬底; 绝缘层，设置有形成在所述半导体衬底上的镶嵌图案; 包含在镶嵌图案的表面上形成的RuO 2层的扩散阻挡层和形成在RuO 2层的两部分上的Al沉积抑制层 大马士革图案的上部; 以及通过MOCVD法在扩散阻挡层上形成的包括Al的布线金属层，以填充镶嵌图案。

公开(公告)号：US20090017619A1

公开(公告)日：2009-01-15

申请号：US12169790

申请日：2008-07-09

申请人： Young Jin LEE ,  Baek Mann KIM ,  Soo Hyun KIM ,  Dong Ha JUNG ,  Jeong Tae KIM ,  Hyeong Tag JEON ,  Keun Woo LEE ,  Keun Jun KIM ,  Tae Yong PARK

发明人： Young Jin LEE ,  Baek Mann KIM ,  Soo Hyun KIM ,  Dong Ha JUNG ,  Jeong Tae KIM ,  Hyeong Tag JEON ,  Keun Woo LEE ,  Keun Jun KIM ,  Tae Yong PARK

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76855

摘要： A metal suicide layer is fabricated in a semiconductor device. A first metal layer is deposited on a silicon substrate formed with an S interlayer dielectric having a contact hole through PVD. A second metal layer is deposited on the first metal layer through any one of CVD and ALD. Annealing is performed on the silicon substrate which is formed with the first and second metal layers to form the metal silicide. The portions of the second metal layer and the first metal layer which have not reacted during annealing are removed.

摘要翻译： 在半导体器件中制造金属硅化物层。 第一金属层沉积在由具有通过PVD的接触孔的S层间电介质形成的硅衬底上。 通过CVD和ALD中的任一种将第二金属层沉积在第一金属层上。 在由第一和第二金属层形成的硅衬底上进行退火以形成金属硅化物。 去除在退火过程中没有反应的第二金属层和第一金属层的部分。

公开(公告)号：US20080157367A1

公开(公告)日：2008-07-03

申请号：US11755390

申请日：2007-05-30

申请人： Soo Hyun KIM ,  Baek Mann KIM ,  Young Jin LEE ,  Dong Ha JUNG ,  Jeong Tae KIM

发明人： Soo Hyun KIM ,  Baek Mann KIM ,  Young Jin LEE ,  Dong Ha JUNG ,  Jeong Tae KIM

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76856 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-layer metal wiring of a semiconductor device and a method for forming the same are disclosed. The multi-layer metal wiring of the semiconductor device includes a lower Cu wiring, and an upper Al wiring formed to be contacted with the lower Cu wiring, and a diffusion barrier layer interposed between the lower Cu wiring and the upper Al wiring. The diffusion barrier layer is formed of a W-based layer.

摘要翻译： 公开了一种半导体器件的多层金属布线及其形成方法。 半导体器件的多层金属布线包括下Cu布线和形成为与下Cu布线接触的上Al布线，以及介于下Cu布线和上Al布线之间的扩散阻挡层。 扩散阻挡层由W基层形成。

公开(公告)号：US20120007240A1

公开(公告)日：2012-01-12

申请号：US13238570

申请日：2011-09-21

申请人： Dong Ha JUNG ,  Baek Mann KIM ,  Soo Hyun KIM ,  Young Jin LEE ,  Sun Woo HWANG ,  Jeong Tae KIM

发明人： Dong Ha JUNG ,  Baek Mann KIM ,  Soo Hyun KIM ,  Young Jin LEE ,  Sun Woo HWANG ,  Jeong Tae KIM

IPC分类号： H01L23/535

CPC分类号： H01L21/76879 ,  H01L21/76831 ,  H01L21/76856 ,  H01L21/76886 ,  H01L21/76888 ,  H01L23/53223 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO2 layer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuO2 layer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.

摘要翻译： 半导体器件的金属布线包括半导体衬底; 绝缘层，设置有形成在所述半导体衬底上的镶嵌图案; 包含在镶嵌图案的表面上形成的RuO 2层的扩散阻挡层和形成在该镶嵌图案的两侧上部的RuO 2层的一部分上的Al沉积抑制层; 以及通过MOCVD法在扩散阻挡层上形成的包括Al的布线金属层，以填充镶嵌图案。

公开(公告)号：US20100193956A1

公开(公告)日：2010-08-05

申请号：US12754776

申请日：2010-04-06

申请人： Soo Hyun KIM ,  Baek Mann KIM ,  Young Jin LEE ,  Dong Ha JUNG ,  Jeong Tae KIM

发明人： Soo Hyun KIM ,  Baek Mann KIM ,  Young Jin LEE ,  Dong Ha JUNG ,  Jeong Tae KIM

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76856 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-layer metal wiring of a semiconductor device and a method for forming the same are disclosed. The multi-layer metal wiring of the semiconductor device includes a lower Cu wiring, and an upper Al wiring formed to be contacted with the lower Cu wiring, and a diffusion barrier layer interposed between the lower Cu wiring and the upper Al wiring. The diffusion barrier layer is formed of a W-based layer.

摘要翻译： 公开了一种半导体器件的多层金属布线及其形成方法。 半导体器件的多层金属布线包括下Cu布线和形成为与下Cu布线接触的上Al布线，以及介于下Cu布线和上Al布线之间的扩散阻挡层。 扩散阻挡层由W基层形成。

公开(公告)号：US20080157368A1

公开(公告)日：2008-07-03

申请号：US11755814

申请日：2007-05-31

申请人： Jeong Tae KIM ,  Baek Mann KIM ,  Soo Hyun KIM ,  Young Jin LEE ,  Dong Ha JUNG

发明人： Jeong Tae KIM ,  Baek Mann KIM ,  Soo Hyun KIM ,  Young Jin LEE ,  Dong Ha JUNG

IPC分类号： H01L21/768 ,  H01L23/538

CPC分类号： H01L21/76846 ,  H01L21/76843 ,  H01L21/76856 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-layered metal line of a semiconductor device has a lower metal line and an upper metal line. The upper metal line includes a diffusion barrier, which is made of a stack of a first WNx layer, a WCyNx layer and a second WNx layer.

摘要翻译： 半导体器件的多层金属线具有下金属线和上金属线。 上部金属线包括扩散阻挡层，该扩散阻挡层由第一WN层X 1层，WC x N N层和/ 第二WN 层。

公开(公告)号：US20080146026A1

公开(公告)日：2008-06-19

申请号：US11776905

申请日：2007-07-12

申请人： Soo Hyun KIM ,  Baek Mann KIM ,  Young Jin LEE ,  Sun Woo HWANG ,  Dong Ha JUNG ,  Jeong Tae KIM

发明人： Soo Hyun KIM ,  Baek Mann KIM ,  Young Jin LEE ,  Sun Woo HWANG ,  Dong Ha JUNG ,  Jeong Tae KIM

IPC分类号： H01L21/44

CPC分类号： H01L21/76826 ,  H01L21/76838 ,  H01L27/10885 ,  H01L27/10888

摘要： A semiconductor memory device is manufactured by: forming a hole by etching an interlayer insulation film formed over a semiconductor substrate; forming a barrier film over the interlayer insulation film including a surface of the hole; forming a first metal film over the barrier film so as to fill in the hole; forming a bit line contact plug in the hole by removing the first metal film and the barrier film so as to expose the interlayer insulation film; carrying out a gas treatment to a surface of the interlayer insulation film including the bit line contact plug so as to promote a growth of metal nucreation; forming a second metal film over the gas treated interlayer insulation film; and forming a bit line in contact with the bit line contact plug by etching the second metal film.

摘要翻译： 半导体存储器件通过：通过蚀刻形成在半导体衬底上的层间绝缘膜来形成孔; 在包括所述孔的表面的所述层间绝缘膜上形成阻挡膜; 在所述阻挡膜上形成第一金属膜以填充所述孔; 通过去除第一金属膜和阻挡膜以形成层间绝缘膜，从而在孔中形成位线接触插塞; 对包含位线接触插塞的层间绝缘膜的表面进行气体处理，以促进金属含量的增长; 在气体处理的层间绝缘膜上形成第二金属膜; 并通过蚀刻第二金属膜形成与位线接触插塞接触的位线。

公开(公告)号：US20090200672A1

公开(公告)日：2009-08-13

申请号：US12427894

申请日：2009-04-22

申请人： Soo Hyun KIM ,  Kwan Yong LIM ,  Baek Mann KIM ,  Young Jin LEE ,  Noh Jung KWAK ,  Hyun Chul SOHN

发明人： Soo Hyun KIM ,  Kwan Yong LIM ,  Baek Mann KIM ,  Young Jin LEE ,  Noh Jung KWAK ,  Hyun Chul SOHN

IPC分类号： H01L23/52 ,  H01L21/336 ,  H01L21/4763

CPC分类号： H01L21/76841 ,  H01L21/28562 ,  H01L27/10873 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method for manufacturing a semiconductor device. This method includes the step of forming a diffusion barrier film, which is interposed between a silicon film and a metal film and functions to prevent diffusion between the silicon and metal films. The diffusion barrier film is formed of a WSixNy film or a WSix film by using an ALD process.

摘要翻译： 公开了半导体器件的制造方法。 该方法包括形成介于硅膜和金属膜之间的扩散阻挡膜的步骤，其功能是防止硅和金属膜之间的扩散。 通过使用ALD工艺，由WSixNy膜或WSix膜形成扩散阻挡膜。

公开(公告)号：US20080081452A1

公开(公告)日：2008-04-03

申请号：US11693137

申请日：2007-03-29

申请人： Soo Hyun KIM ,  Noh Jung KWAK ,  Baek Mann KIM ,  Young Jin LEE ,  Sun Woo HWANG ,  Kwan Yong LIM

发明人： Soo Hyun KIM ,  Noh Jung KWAK ,  Baek Mann KIM ,  Young Jin LEE ,  Sun Woo HWANG ,  Kwan Yong LIM

IPC分类号： H01L21/3205

CPC分类号： H01L21/28061 ,  H01L29/4941

摘要： A tungsten polymetal gate is made by forming a gate insulation layer and a polysilicon layer on a semiconductor substrate; depositing a barrier layer on the polysilicon layer; depositing a tungsten nucleation layer on the barrier layer through an ALD process; depositing a tungsten layer on the tungsten nucleation layer through a CVD process; depositing a hard mask layer on the tungsten layer; and etching the hard mask layer, the tungsten layer, the tungsten nucleation layer, the barrier layer, the polysilicon layer, and the gate insulation layer.

摘要翻译： 通过在半导体衬底上形成栅极绝缘层和多晶硅层来制造钨多金属栅极; 在所述多晶硅层上沉积阻挡层; 通过ALD工艺在阻挡层上沉积钨成核层; 通过CVD工艺在钨成核层上沉积钨层; 在钨层上沉积硬掩模层; 并且蚀刻硬掩模层，钨层，钨成核层，势垒层，多晶硅层和栅极绝缘层。