-
1.发明申请公开(公告)号：US20060150133A1
公开(公告)日：2006-07-06
申请号：US11274556
申请日：2005-11-15
CPC分类号： G06F17/5031 , G06F17/505
摘要： A circuit design method, computer program product and chip design system embodying the method. A gate selected for static timing analysis (STA) from a circuit design. Initial performance characteristics (e.g., load and transition slew) are determined for the selected gate. A charge equivalent effective capacitance (CQeff) is determined for the gate from the initial performance characteristics. A gate delay is determined in a single pass for the gate using CQeff as an effective load for said selected gate. Optionally, if the total gate load capacitance (Ctot) exceeds CQeff by less than a minimum, the effective capacitance (Ceff) is determined and used for determining the gate delay instead.
摘要翻译： 电路设计方法，计算机程序产品和芯片设计系统体现了该方法。 从电路设计中选择静态时序分析（STA）的门。 为所选择的门确定初始性能特征（例如负载和转换转换）。 从初始性能特性确定栅极的电荷等效有效电容（C QEff）。 门使用C QEff 作为所选择的门的有效负载，在门的单次通过中确定门延迟。 可选地，如果总栅极负载电容（C SUB）大于最小值，则有效电容（C eff）为 确定并用于确定门延迟。
-
2.发明授权公开(公告)号：US07552412B2
公开(公告)日：2009-06-23
申请号：US11274556
申请日：2005-11-15
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505
摘要： A circuit design method, computer program product and chip design system embodying the method. A gate selected for static timing analysis (STA) from a circuit design. Initial performance characteristics (e.g., load and transition slew) are determined for the selected gate. A charge equivalent effective capacitance (CQeff) is determined for the gate from the initial performance characteristics. A gate delay is determined in a single pass for the gate using CQeff as an effective load for said selected gate. Optionally, if the total gate load capacitance (Ctot) exceeds CQeff by less than a minimum, the effective capacitance (Ceff) is determined and used for determining the gate delay instead.
摘要翻译： 电路设计方法，计算机程序产品和芯片设计系统体现了该方法。 从电路设计中选择静态时序分析（STA）的门。 为所选择的门确定初始性能特征（例如负载和转换转换）。 从初始性能特性确定栅极的电荷等效有效电容（CQeff）。 在使用CQeff作为所选择的栅极的有效负载的栅极的单次通过中确定栅极延迟。 可选地，如果总栅极负载电容（Ctot）超过CQeff小于最小值，则确定有效电容（Ceff）并用于确定栅极延迟。
-
公开(公告)号：US20120124542A1
公开(公告)日：2012-05-17
申请号：US12944480
申请日：2010-11-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/80 , G06F2217/84
摘要： A method for optimizing a circuit includes at least a first branch and a second branch includes defining an objective function using a shape of waveforms measured at a timing point in each branch, and optimizing the objective function to minimize a variance of clock skew of the first branch and the second branch across different process voltage temperature values.
摘要翻译： 一种用于优化电路的方法包括至少第一分支和第二分支，包括使用在每个分支中的定时点测量的波形的形状来定义目标函数，以及优化目标函数以最小化第一分支的时钟偏差的方差 分支和第二分支横跨不同的过程电压温度值。
-
公开(公告)号：US20120123725A1
公开(公告)日：2012-05-17
申请号：US12944892
申请日：2010-11-12
IPC分类号： G06F19/00
CPC分类号： G06F17/5036
摘要： A computer-implemented system, method, and storage device simulate a periodic voltage waveform in a network model of the integrated circuit design. The method then determines resultant current values in each segment of nets of the integrated circuit design resulting from the periodic voltage waveform and performs a Fourier transform of the periodic voltage waveform to generate a frequency domain representation of the periodic voltage waveform. The frequency domain representation comprises multiple Fourier terms, each of the Fourier terms is a frequency that is a multiple of the base frequency. Next, the method performs an AC analysis of the resultant voltage at each frequency of the multiple Fourier terms. The AC analysis provides an electrical current value for each of the frequencies of the Fourier terms for each of the nets. This allows the method to compute a root mean square current through each of the nets based on the AC analysis. Then, the method determines whether the root mean square current for any of the segments of the nets exceeds a current limit, and reports any segment of the nets for which the root mean square current exceeds the current limit.
摘要翻译： 计算机实现的系统，方法和存储设备模拟集成电路设计的网络模型中的周期性电压波形。 然后，该方法确定由周期性电压波形产生的集成电路设计的网络的每个段中的合成电流值，并执行周期性电压波形的傅里叶变换以产生周期性电压波形的频域表示。 频域表示包括多个傅立叶项，每个傅立叶项是基频的倍数的频率。 接下来，该方法对多傅里叶项的每个频率进行所得到的电压的AC分析。 AC分析为每个网络的傅立叶项的每个频率提供电流值。 这允许该方法基于AC分析来计算通过每个网络的均方根电流。 然后，该方法确定网络的任何段的均方根电流是否超过电流限制，并且报告均方根电流超过电流极限的网络的任何段。
-
5.发明申请公开(公告)号：US20090077515A1
公开(公告)日：2009-03-19
申请号：US11855323
申请日：2007-09-14
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A preliminary static timing analysis run is performed to calculate the delay and slew as well as timing windows for each net in the design, followed by coupling analysis for each given aggressor-victim combination, and to calculate the noise effect on the timing of victim net. Given a set of functional groups that relate the coupled aggressors to each other, the worst set of aggressors are calculated that satisfy the constraints from the functional groups, based on the calculated impact of each aggressor on the victim. Similarly the set of aggressors which contribute to the maximum amount of inductive coupling noise effect on timing are calculated. Furthermore, the coupling noise impact of the reduced set of aggressors on the given victim line and adjust the delay value calculated in the preliminary static timing analysis run.
摘要翻译： 执行初步静态时序分析运行，以计算设计中每个网络的延迟和摆动以及定时窗口，然后针对每个给定的攻击者 - 受害者组合进行耦合分析，并计算对受害者网络时间的噪声影响 。 给定一组使耦合的侵略者相互关联的功能组，根据每个侵略者对受害者的计算影响，计算出最差的攻击者集合，以满足功能组的限制。 类似地，计算有助于最大量的电感耦合噪声对定时影响的侵略者集合。 此外，减少的攻击者集合对给定的受害者线路的耦合噪声影响，并调整在初步静态时序分析运行中计算的延迟值。
-
公开(公告)号：US08396910B2
公开(公告)日：2013-03-12
申请号：US12265765
申请日：2008-11-06
申请人： Soroush Abbaspour , Peter Feldmann , Safar Hatami
发明人： Soroush Abbaspour , Peter Feldmann , Safar Hatami
IPC分类号： G06F7/00
CPC分类号： H03M7/30
摘要： A system and method for waveform compression includes preprocessing a collection of waveforms representing cell and/or interconnect response waveforms and constructing a representative waveform basis using linear algebra to create basis waveforms for a larger set of waveforms. The collection waveforms are represented as linear combination coefficients of an adaptive subset of the basis waveforms to compress an amount of stored information needed to reproduce the collection of waveforms. The representation of coefficients may be further compressed by, e.g., analytic representation.
摘要翻译： 用于波形压缩的系统和方法包括预处理表示单元和/或互连响应波形的波形的集合，并使用线性代数构建代表性的波形基础，以创建更大的一组波形的基本波形。 收集波形被表示为基本波形的自适应子集的线性组合系数，以压缩再现波形收集所需的存储信息量。 可以通过例如分析表示来进一步压缩系数的表示。
-
公开(公告)号：US08359563B2
公开(公告)日：2013-01-22
申请号：US12542042
申请日：2009-08-17
CPC分类号： G06F17/5031 , G06F2217/84
摘要： In one embodiment, the invention is a moment-based characterization waveform for static timing analysis. One embodiment of a method for mapping a timing waveform associated with a gate of an integrated circuit to a characterization waveform includes using a processor to perform steps including: computing one or more moments of the timing waveform and defining the characterization waveform in accordance with the moments.
摘要翻译： 在一个实施例中，本发明是用于静态时序分析的基于时刻的表征波形。 用于将与集成电路的栅极相关联的定时波形映射到表征波形的方法的一个实施例包括使用处理器执行步骤，包括：计算定时波形的一个或多个时刻并根据时刻定义表征波形 。
-
8.发明授权Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuits 有权在VLSI电路定时抽取过程中采用与摆率相关的引脚电容捕获互连寄生效应的方法公开(公告)号：US08103997B2
公开(公告)日：2012-01-24
申请号：US12426492
申请日：2009-04-20
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036 , G06F2217/84
摘要： A method for converting interconnect parasitics of an interconnect network into slew dependent pin capacitances utilizes charge matching between predetermined voltage thresholds. During timing abstraction of a macro, parasitics of interconnects connected to the primary inputs are represented as slew dependent pin capacitances in an abstract model being created. Interconnect model order reduction is employed to speed the process. The generated abstract is subsequently used in place of each occurrence of the macro during chip level hierarchical static timing analysis, leading to an enhanced accuracy of the timing analysis of the logic components driving the abstracts.
摘要翻译： 用于将互连网络的互连寄生效应转换成与转换相关的引脚电容的方法利用预定电压阈值之间的电荷匹配。 在宏的定时抽象期间，连接到主输入的互连的寄生效应在被创建的抽象模型中被表示为与电压相关的引脚电容。 采用互连模型订单减少来加速流程。 在芯片级分层静态时序分析期间，随后使用生成的抽象代替宏的每次出现，从而提高驱动摘要的逻辑组件的时序分析的精度。
-
9.发明申请Method of Employing Slew Dependent Pin Capacitances to Capture Interconnect Parasitics During Timing Abstraction of VLSI Circuits 有权在定时抽取VLSI电路的过程中采用压摆相关引脚电容捕获互连寄生的方法公开(公告)号：US20100269083A1
公开(公告)日：2010-10-21
申请号：US12426492
申请日：2009-04-20
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036 , G06F2217/84
摘要： A method for converting interconnect parasitics of an interconnect network into slew dependent pin capacitances utilizes charge matching between predetermined voltage thresholds. During timing abstraction of a macro, parasitics of interconnects connected to the primary inputs are represented as slew dependent pin capacitances in an abstract model being created. Interconnect model order reduction is employed to speed the process. The generated abstract is subsequently used in place of each occurrence of the macro during chip level hierarchical static timing analysis, leading to an enhanced accuracy of the timing analysis of the logic components driving the abstracts.
摘要翻译： 用于将互连网络的互连寄生效应转换成与转换相关的引脚电容的方法利用预定电压阈值之间的电荷匹配。 在宏的定时抽象期间，连接到主输入的互连的寄生效应在被创建的抽象模型中被表示为与电压相关的引脚电容。 采用互连模型订单减少来加速流程。 在芯片级分层静态时序分析期间，随后使用生成的抽象代替宏的每次出现，从而提高驱动摘要的逻辑组件的时序分析的精度。
-
10.发明申请ARBITRARY WAVEFORM PROPAGATION THROUGH A LOGIC GATE USING TIMING ANALYSIS RESULTS 有权通过使用时序分析结果的逻辑门进行仲裁波形传播公开(公告)号：US20090228851A1
公开(公告)日：2009-09-10
申请号：US12044223
申请日：2008-03-07
申请人： Soroush Abbaspour , Peter Feldmann
发明人： Soroush Abbaspour , Peter Feldmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： An approach for performing arbitrary waveform propagation through a logic gate using timing analysis results is described. In one embodiment, there is an arbitrary waveform propagation tool for determining an effect of noise on a digital integrated circuit having at least one logic gate. A timing analysis component is configured to perform a timing analysis on the at least one logic gate and a noise analysis component is configured to perform a noise analysis. A waveform propagation model synthesizer component is configured to dynamically synthesize a waveform propagation model as a function of the timing analysis. The waveform propagation model synthesizer component is further configured to apply an arbitrary voltage waveform comprising one of a noisy waveform or noise glitch waveform and determine an effect of the arbitrary voltage waveform on the at least one logic gate from the dynamically synthesized waveform propagation model.
摘要翻译： 描述了使用定时分析结果通过逻辑门执行任意波形传播的方法。 在一个实施例中，存在用于确定噪声对具有至少一个逻辑门的数字集成电路的影响的任意波形传播工具。 定时分析部件被配置为对所述至少一个逻辑门执行定时分析，并且噪声分析部件被配置为执行噪声分析。 波形传播模型合成器组件被配置为动态地合成作为时序分析的函数的波形传播模型。 波形传播模型合成器部件还被配置为施加包括噪声波形或噪声毛刺波形中的一个的任意电压波形，并且从动态合成的波形传播模型确定任意电压波形对至少一个逻辑门的影响。
-
-
-
-
-
-
-
-
-
搜索结果
33 条记录 (耗时 0.019 秒)