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    Method and apparatus for resorting a sequence of sorted strings
    7.
    发明授权
    Method and apparatus for resorting a sequence of sorted strings 失效
    排序字符串序列的方法和装置

    公开(公告)号：US08549023B2

    公开(公告)日：2013-10-01

    申请号：US12274425

    申请日：2008-11-20

    申请人： Yu Guo ,  Qi Lu ,  Jin Zhu ,  Zhi Bo Zuo

    发明人： Yu Guo ,  Qi Lu ,  Jin Zhu ,  Zhi Bo Zuo

    IPC分类号： G06F7/00

    CPC分类号： G06F17/30985

    摘要： A method and apparatus for resorting a sequence of sorted strings, wherein the sequence of sorted strings is obtained by sorting a plurality of strings based on a first character collation standard and the resorting is based on a second character collation standard. A method in accordance with an embodiment of the invention includes: comparing the first character collation standard with the second character collation standard to obtain a change of the character collation standard; and resorting the sequence of sorted strings based on the change of the character collation standard. The method of the present invention takes the change of the character collation standard and its affection to the sequence of sorted strings into consideration, and can resort the sequence of sorted strings quickly and thus save time for resorting.

    摘要翻译： 一种用于排序排序的字符串序列的方法和装置，其中通过基于第一字符对照标准对多个字符串进行排序来获得排序字符串的序列，并且所述提取是基于第二字符归类标准。 根据本发明的实施例的方法包括：将第一字符校对标准与第二字符校对标准进行比较以获得字符校对标准的改变; 并根据字符归类标准的改变来求排序的字符串序列。 本发明的方法考虑到字符对照标准的改变及其对排序字符序列的影响，并且可以快速地排序排序的字符串，从而节省诉求时间。

    Adaptive precision arithmetic unit for error tolerant applications
    9.
    发明授权
    Adaptive precision arithmetic unit for error tolerant applications 有权
    用于容错应用的自适应精密算术单元

    公开(公告)号：US08438207B2

    公开(公告)日：2013-05-07

    申请号：US11864580

    申请日：2007-09-28

    申请人： Josephine Ammer Bolotski ,  Jenny Bui ,  Qi Lu

    发明人： Josephine Ammer Bolotski ,  Jenny Bui ,  Qi Lu

    IPC分类号： G06F7/52

    CPC分类号： G06G7/16 ,  G06F17/10 ,  H03H17/0223 ,  H03H17/06

    摘要： Two process-tolerant arithmetic circuit architectures are implemented to develop functional blocks for error-tolerant applications such as FIR filters and FFT blocks. The resulting blocks may achieve computational performance of up to 42 times higher than conventional architectures. Embodiments adaptively change the precision of the computation to achieve a high precision computation given the underlying speed of the circuit. The resulting improvement can be allocated to increasing yield or dynamically trading off between reduced power consumption, faster computation, or higher-fidelity computation.

    摘要翻译： 实现两个容错算术电路架构来开发诸如FIR滤波器和FFT块之类的容错应用的功能块。 所得到的块可以实现高达传统架构的42倍的计算性能。 给定电路的底层速度，实施方式自适应地改变计算的精度以实现高精度计算。 所得到的改进可以被分配用于在降低的功率消耗，更快的计算或更高保真度的计算之间提高产量或动态地折中。