公开(公告)号：US20120068302A1

公开(公告)日：2012-03-22

申请号：US13228099

申请日：2011-09-08

申请人： Stefan Beierke ,  Johann Gross

发明人： Stefan Beierke ,  Johann Gross

IPC分类号： H01L27/06 ,  H01L21/50 ,  H01L23/48

CPC分类号： G06K19/07754 ,  H01L2924/0002 ,  H05K1/181 ,  H01L2924/00

摘要： An electronic device including a semiconductor die, which has a top surface that is configured to operate as a printed circuit board so as to provide connections for at least one passive component, in particular a passive surface mounted device (SMD).

摘要翻译： 一种包括半导体管芯的电子器件，其具有被配置为作为印刷电路板操作以便提供用于至少一个无源部件的连接的顶表面，特别是被动表面安装器件（SMD）。

公开(公告)号：US06069808A

公开(公告)日：2000-05-30

申请号：US81738

申请日：1998-05-19

申请人： Issa Mahboobi S. Panahi ,  Stefan Beierke

发明人： Issa Mahboobi S. Panahi ,  Stefan Beierke

IPC分类号： H02M7/5387 ,  H02P27/08 ,  H02M3/24

CPC分类号： H02M7/53875 ,  H02M2007/53876

摘要： A control apparatus for controlling a three phase load apparatus. The control apparatus includes a voltage source inverter having a first pair of transistors, a second pair of transistors, and a third pair of transistors. Each such pair of transistors is connected serially between the terminals of a voltage source. The activation of a first transistor in each such pair of such transistors is effected by the application thereto of a first activation voltage, a second activation voltage and a third activation voltage, respectively, causing a first phase voltage, a second phase voltage and a third phase voltage, to be applied to a respective one of the three parts of the three-phase load apparatus. The selection and duration of activation of such first transistors during each of a continuing series of equal time periods T.sub.p is symmetrical about the mid-point of each of the time periods, and is represented by six non-zero vectors and two zero vectors. The control apparatus also includes a processor, and a bus coupled to the processor for communicating data between the processor and other control apparatus elements. The control apparatus also includes a counter coupled to the bus for providing a counter value counting from zero up to a value of one half of T.sub.p and then counting down to zero, for each of the equal time periods T.sub.p. A compare unit is also included, coupled to the bus, having a plurality of registers for the storage of transition count values corresponding to the transition times between the activations of the first transistors in accordance with predetermined space vectors, for comparing the counter value against the transition count values and providing respective transition timing signals when the counter value is the same as the transition count values. Finally, a state machine is included, coupled to the bus and to the compare unit for generating the first activation voltage, the second activation voltage and the third activation voltage and providing them to the voltage source inverter in response to the respective transition timing signals.