公开(公告)号：US07034610B2

公开(公告)日：2006-04-25

申请号：US10861379

申请日：2004-06-07

申请人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

发明人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

IPC分类号： H03F1/14

CPC分类号： H03G3/001 ,  H03G1/0088

摘要： An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

摘要翻译： 上游放大器集成在具有数模转换器（DAC）的基板上，以形成集成电路。 在一个实施例中，低通滤波器也集成在基板上。 上游放大器的输出信号电平是可控的。 在实施例中，通过改变DAC的偏置电流对上游放大器的输出信号电平进行微调。 软件控制位用于在上电操作模式和掉电操作模式之间切换。 上游放大器以突发模式发送。 上游放大器的功耗随放大器的输出信号电平而变化。 在上游放大器的正和负路径之间达到高度的匹配。 这提供了诸如衬底噪声，时钟刺激和由增益变化引起的毛刺等共模干扰的高抗扰性。

公开(公告)号：US08013768B2

公开(公告)日：2011-09-06

申请号：US10163313

申请日：2002-06-07

申请人： Stephen A Jantzi ,  Anilkumar V Tammineedi ,  Jungwoo Song ,  Lawrence M Burns ,  Donald G McMullin ,  Agnes N Woo

发明人： Stephen A Jantzi ,  Anilkumar V Tammineedi ,  Jungwoo Song ,  Lawrence M Burns ,  Donald G McMullin ,  Agnes N Woo

IPC分类号： H03M1/66

CPC分类号： H03G3/001 ,  H03G1/0088

摘要： An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

摘要翻译： 上游放大器集成在具有数模转换器（DAC）的基板上，以形成集成电路。 在一个实施例中，低通滤波器也集成在基板上。 上游放大器的输出信号电平是可控的。 在实施例中，通过改变DAC的偏置电流对上游放大器的输出信号电平进行微调。 软件控制位用于在上电操作模式和掉电操作模式之间切换。 上游放大器以突发模式发送。 上游放大器的功耗随放大器的输出信号电平而变化。 在上游放大器的正和负路径之间达到高度的匹配。 这提供了诸如衬底噪声，时钟刺激和由增益变化引起的毛刺等共模干扰的高抗扰性。

公开(公告)号：US06747510B2

公开(公告)日：2004-06-08

申请号：US10163143

申请日：2002-06-07

申请人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

发明人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

IPC分类号： H03F152

CPC分类号： H03G3/001 ,  H03G1/0088

摘要： An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

摘要翻译： 上游放大器集成在具有数模转换器（DAC）的基板上，以形成集成电路。 在一个实施例中，低通滤波器也集成在基板上。 上游放大器的输出信号电平是可控的。 在实施例中，通过改变DAC的偏置电流对上游放大器的输出信号电平进行微调。 软件控制位用于在上电操作模式和掉电操作模式之间切换。 上游放大器以突发模式发送。 上游放大器的功耗随放大器的输出信号电平而变化。 在上游放大器的正和负路径之间达到高度的匹配。 这提供了诸如衬底噪声，时钟刺激和由增益变化引起的毛刺等共模干扰的高抗扰性。

公开(公告)号：US08334721B2

公开(公告)日：2012-12-18

申请号：US13226233

申请日：2011-09-06

申请人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

发明人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

IPC分类号： H03F1/14

CPC分类号： H03G3/001 ,  H03G1/0088

摘要： An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

摘要翻译： 上游放大器集成在具有数模转换器（DAC）的基板上，以形成集成电路。 在一个实施例中，低通滤波器也集成在基板上。 上游放大器的输出信号电平是可控的。 在实施例中，通过改变DAC的偏置电流对上游放大器的输出信号电平进行微调。 软件控制位用于在上电操作模式和掉电操作模式之间切换。 上游放大器以突发模式发送。 上游放大器的功耗随放大器的输出信号电平而变化。 在上游放大器的正和负路径之间达到高度的匹配。 这提供了诸如衬底噪声，时钟刺激和由增益变化引起的毛刺等共模干扰的高抗扰性。

公开(公告)号：US20120086592A1

公开(公告)日：2012-04-12

申请号：US13226233

申请日：2011-09-06

申请人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Anges N. Woo

发明人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Anges N. Woo

IPC分类号： H03M1/66

CPC分类号： H03G3/001 ,  H03G1/0088

摘要： An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

摘要翻译： 上游放大器集成在具有数模转换器（DAC）的基板上，以形成集成电路。 在一个实施例中，低通滤波器也集成在基板上。 上游放大器的输出信号电平是可控的。 在实施例中，通过改变DAC的偏置电流对上游放大器的输出信号电平进行微调。 软件控制位用于在上电操作模式和掉电操作模式之间切换。 上游放大器以突发模式发送。 上游放大器的功耗随放大器的输出信号电平而变化。 在上游放大器的正和负路径之间达到高度的匹配。 这提供了诸如衬底噪声，时钟刺激和由增益变化引起的毛刺等共模干扰的高抗扰性。

公开(公告)号：US08963236B2

公开(公告)日：2015-02-24

申请号：US13714396

申请日：2012-12-13

申请人： Jungwoo Song ,  Jaekyu Lee

发明人： Jungwoo Song ,  Jaekyu Lee

IPC分类号： H01L27/105 ,  H01L27/10 ,  H01L27/22 ,  H01L45/00 ,  H01L27/24 ,  H01L27/02

CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L27/0203 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L29/4236 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are data storage devices and methods of manufacturing the same. The device may include a plurality of cell selection parts formed in a substrate, a plate conductive pattern covering the cell selection parts and electrically connected to first terminals of the cell selection parts, a plurality of through-pillars penetrating the plate conductive pattern and insulated from the plate conductive pattern, and a plurality of data storage parts directly connected to the plurality of through-pillars, respectively. The data storage parts may be electrically connected to second terminals of the cell selection parts, respectively.

摘要翻译： 提供数据存储装置及其制造方法。 该器件可以包括形成在衬底中的多个电池选择部件，覆盖电池选择部分并电连接到电池选择部件的第一端子的板状导电图案，穿过板状导电图案并与之绝缘的多个贯通柱 板状导电图案，以及分别与多个贯通柱直接连接的多个数据存储部。 数据存储部分可以分别电连接到小区选择部分的第二终端。

公开(公告)号：US08705752B2

公开(公告)日：2014-04-22

申请号：US11523693

申请日：2006-09-20

申请人： Xicheng Jiang ,  Jungwoo Song ,  Jianlong Chen

发明人： Xicheng Jiang ,  Jungwoo Song ,  Jianlong Chen

IPC分类号： H04R5/00

CPC分类号： H04R3/04

摘要： A noise reduction circuit for reducing the effects of low frequency noise such as wind noise in communications applications is described. In one embodiment, the noise reduction circuit features a high pass filter formed by exploiting the existing off-chip AC coupling capacitances in making the connection to the source of audio signals. The filter may be adaptive to environmental low frequency noise level through programming the shunt resistances. A low-noise wide dynamic range programmable gain amplifier is also described. Adaptive equalization of the audio signal is also described through the utilization of programmable front-end resistors and a back-end audio equalizer.

摘要翻译： 描述了用于降低通信应用中诸如风噪声的低频噪声的影响的降噪电路。 在一个实施例中，噪声降低电路具有通过利用现有的片外AC耦合电容在形成与音频信号源的连接而形成的高通滤波器。 滤波器可以通过编程分流电阻来适应环境低频噪声电平。 还描述了低噪声宽动态范围可编程增益放大器。 还通过利用可编程前端电阻和后端音频均衡器来描述音频信号的自适应均衡。

公开(公告)号：US07547956B2

公开(公告)日：2009-06-16

申请号：US10975090

申请日：2004-10-28

申请人： Derek Tam ,  Jasmine Cheng ,  Jungwoo Song ,  Takayuki Hayashi

发明人： Derek Tam ,  Jasmine Cheng ,  Jungwoo Song ,  Takayuki Hayashi

IPC分类号： H01L23/58

CPC分类号： H01L29/93 ,  H01L29/94 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/18

摘要： A circuit with dielectric thicknesses is presented that includes a low-pass filter including one or more semiconductor devices having a thick gate oxide layer, while further semiconductor devices of the circuit have thin gate oxide layers. The low-pass filter semiconductor device includes an N-type substrate, a P-type region formed on the N-type substrate, a thick gate oxide layer formed over the P-type region, a P+ gate electrode formed over the thick gate oxide layer and coupled to a first voltage supply line, and P+ pick-up terminals formed in the P-type region adjacent the gate electrode and coupled to a second voltage supply line. The low-pass filter semiconductor device acts as a capacitor, whereby a gate-to-substrate voltage is maintained at less than zero volts to maintain a stable control voltage for the circuit.

摘要翻译： 提出了具有介电厚度的电路，其包括包括具有厚栅极氧化物层的一个或多个半导体器件的低通滤波器，而该电路的另外的半导体器件具有薄的栅极氧化物层。 低通滤波器半导体器件包括N型衬底，形成在N型衬底上的P型区，在P型区上形成的厚栅氧化层，形成在厚栅极氧化物上的P +栅电极 并且耦合到第一电压供应线，以及P +拾取端子，其形成在与栅电极相邻的P型区域中并且耦合到第二电压供应线。 低通滤波器半导体器件用作电容器，由此栅极至衬底的电压保持在小于零伏特以保持电路的稳定的控制电压。

公开(公告)号：US20050156219A1

公开(公告)日：2005-07-21

申请号：US10759076

申请日：2004-01-20

申请人： Chun-ying Chen ,  Jungwoo Song

发明人： Chun-ying Chen ,  Jungwoo Song

IPC分类号： H01L27/108 ,  H01L29/78

CPC分类号： H01L29/78

摘要： A first MOS-on-NWELL device is formed on a substrate and has its pickup terminals optionally connected together. A second MOS-on-NWELL device is formed on the substrate and has its pickup terminals optionally connected together. A gate of the first MOS-on-NWELL device is connected to the pickup terminals of the second MOS-on-NWELL device. A gate of the second MOS-on-NWELL device is connected to the pickup terminals of the first MOS-on-NWELL device. A first PMOS transistor is formed on a substrate and has its source and drain terminals connected together. A second PMOS transistor is formed on a substrate and has its source and drain terminals connected together. A gate of the first PMOS transistor is connected to the source and drain terminals of the second PMOS transistor. A gate of the second PMOS transistor is connected to the source and drain terminals of the first PMOS transistor. A combination of the first and second PMOS transistors are connected in parallel with the first and second MOS-on-NWELL devices.

摘要翻译： 第一MOS-on-NWELL器件形成在衬底上并且其拾取端子可选地连接在一起。 第二个MOS-on-NWELL器件形成在衬底上，并且其拾取端可选地连接在一起。 第一MOS-on-NWELL装置的栅极连接到第二MOS-on-NWELL装置的拾取端。 第二MOS-on-NWELL装置的栅极连接到第一MOS-on-NWELL装置的拾取端。 第一PMOS晶体管形成在衬底上并且其源极和漏极端子连接在一起。 第二PMOS晶体管形成在衬底上并且其源极和漏极端子连接在一起。 第一PMOS晶体管的栅极连接到第二PMOS晶体管的源极和漏极端子。 第二PMOS晶体管的栅极连接到第一PMOS晶体管的源极和漏极端子。 第一和第二PMOS晶体管的组合与第一和第二MOS-on-NWELL器件并联连接。

公开(公告)号：US06828654B2

公开(公告)日：2004-12-07

申请号：US10026470

申请日：2001-12-27

申请人： Derek Tam ,  Jasmine Cheng ,  Jungwoo Song ,  Takayuki Hayashi

发明人： Derek Tam ,  Jasmine Cheng ,  Jungwoo Song ,  Takayuki Hayashi

IPC分类号： H01L2900

CPC分类号： H01L29/93 ,  H01L29/94 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/18

摘要： In a low-pass filter for a phase locked loop (PLL) circuit, a capacitor formed by an N-type substrate, a P-type region formed on the N-type substrate, a thick oxide formed over the P-type region, a P+ gate electrode formed over the thick oxide and coupled to a first voltage supply line, and P+ pick-up terminals formed in the P-type region adjacent the gate electrode and coupled to a second voltage supply line, whereby a gate-to-substrate voltage is maintained at less than zero volts to maintain a stable control voltage for the PLL.

摘要翻译： 在用于锁相环（PLL）电路的低通滤波器中，由N型衬底形成的电容器，形成在N型衬底上的P型区域，形成在P型区域上的厚氧化物， 形成在厚氧化物上并耦合到第一电压供应线的P +栅电极和形成在与栅电极相邻的P型区域中并耦合到第二电压线的P +拾取端子， 由此栅极到衬底的电压保持在小于零伏特以保持PLL的稳定的控制电压。